JVC TH-A5 Service Manual page 16

TH-A5
ZiVA-5 (U8) : DVD controller
1. Pin layout
157
DAI-DATA
158
DAI-BCK/SYSCLKBP
159
DAI-LRCK/IEC958BP
160
I C_CL
2
161
I C_DA
2
162
RTS1
163
RXD1
164
TXD1
165
CTS1
166
VSS
167
VDD_3.3
168
SD-DATA7
169
SD-DATA6
170
SD-DATA5
171
SD-DATA4
172
VSS
173
VDDC
174
SD-DATA3
175
SD-DATA2
176
SD-DATA1
177
SD-DATA0
178
SD-REQ
179
SD-EN
180
VSS
181
VDD_3.3
182
SD-ERROR
183
SD-CLK
184
VSYNC/HIRQ1
185
RTS2/SPI_CLK
186
RXD2/SPI_MISO
187
TXD2/SPI_MOSI
188
CTS2/SPI_CS
189
VDD_5
190
HCS4
191
HCS3
192
HCS2
193
HCS1
194
HCS0
195
VSS
196
VDD_3.3
197
TRST
198
TDO
199
TDI
200
TMS
201
TCK
202
RESET
203
ALE
204
VSS
205
VDDC
206
HAD3
207
HAD2
208
VSS
2. Pin function
Name
RESET
VCLK
XOUT
XIN/bypass clk_216
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-16
1
Description
Pin No. Type
Active Low Reset. Assert for at least 5-milliseconds in the presence of
202 I
clock to reset the entire chip.
Video clock that outputs 27 MHz.
105 I/O
Crystal output. When the internal DCXO is used, a 13.5 MHz crystal
138 O
should be con-nected between this pin and the XIN pin.
Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should
139 I
be con-nected between this pin and the XOUT pin. When an external
oscillator or VCXO is used, its output should be connected to this pin.
When configured for an external bypass clock, a 216 MHz clock should be
connected to this pin. The frequency of an external VCXO can be either 27
or 13.5 MHz.
VDD_3.3
104
VSS
103
MDATA31
102
MDATA30
101
MDATA29
100
MDATA28
99
VDD_3.3
98
MDQM3
97
VSS
96
MDATA27
95
MDATA26
94
MDATA25
93
MDATA24
92
MDATA23
91
MDATA22
90
MDATA21
89
MDATA20
88
VDD_3.3
87
MDQM2
86
VSS
85
MDATA19
84
MDATA18
83
MDATA17
82
MDATA16
81
VDDC
80
VSS
79
MDATA15
78
MDATA14
77
MDATA13
76
MDATA12
75
VDD_3.3
74
MDQM1
73
VSS
72
MDATA11
71
MDATA10
70
MDATA9
69
MDATA8
68
MDATA7
67
MDATA6
66
MDATA5
65
MDATA4
64
VDD_3.3
63
MDQM0
62
VSS
61
MDATA3
60
MDATA2
59
MDATA1
58
MDATA0
57
MCLK
56
VDD_3.3
55
VSS
54
MWE
53
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