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3. Technical Brief
E. PLL Block
The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency
detector with a charge pump with programmable output current. Channel frequency selection and
transmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and the
prescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns with
MD bits to be synchronized with the XO signal.
Figure 3-7-4 shows a block diagram of the PLL block.
PHDOUT
From XO
PS
VCCPHD
GNDPHD
I
PHD
6
CHARGE
PUMP
PHASE
PRESCALER
DETECTOR
PULSE
SKIP
TBL
N
DETECTOR
NPS
DELAY PHD/CP PRE
BIAS CIRCUITS
Figure 3-7-4. Block diagram of the PLL part
- 82 -
MD
2
DELAY
7
offset
MODA
MODB
MODC
MODD
From VCO
VCCPRE
GNDPRE
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