LG U8550 Service Manual page 37

3. Technical Brief
G. U8550 Bluetooth Schematic
CLKREQ
RESOUT2n
UARTRTS3
UARTCTS3
UARTRX3
UARTTX3
PCMDATB
PCMSYN
PCMCLK
PCMDATA
MCLK
RTCCLK
VBT
C646
0.1u
Figure 3-1-11. Schematic of Bluetooth module (BGB202/S2)
• Clock
- Clock request
→ Connected to CLKREQ of MARITA and VINCENNE, input to WOPY
- Fast clock : 13MHz
→ Supplied MCLK from WOPY
→ Frequency deviation : ±10ppm
→ If level of MCLK is less than 400mVpp, connect to 1.8V through R652(120K)
- Slow clock : 32.768kHz
→ Supplied RTCCLK from MARITA
• Power
- Supplied 2.85V from external regulator (U510, controlled by GPIO34 of MARITA)
→ NRESET, UART, PCM, GPIO[2-9]
- 1.8V is generated by internal regulator of BGB202/S2
→ Baseband core, GPIO[10-14], SysClkReq, JTAG
• Reset
- RESOUT2n signal of MARITA controls BGB202/S2 reset.
• UART
- Connected to UART3 of MARITA
- HCI interface between MARITA and BGB202/S2
• PCM
- Audio signal interface between MARITA/VINCENNE and BGB202/S2
• ANT
- 2.4GHz, 50 ohm matching
- Antenna switch(CN601) is used for Bluetooth calibration
U604 BGB202_S2
R650 22K 25
GPIO10 GP_CLK
REF_CLK
R651 0 45
RESET_N TCK_JTAG
TMS_JTAG
TDI_JTAG
44
GPIO2_CTS_UART TDO_JTAG
41
GPIO3_RTS_UART
43
GPIO4_TXD_UART GPIO0
42
GPIO5_RXD_UART GPIO1
35
GPIO6_DA_IP
33
GPIO7_FSC_IP ANT
36
GPIO8_DCLK_IP VANLI
34
GPIO9_DB_IP VANLO
VBAT
C643 100p 29
XTAL1_SYS
R652 120K 28
XTAL2_SYS GND1
120K
GND2
C642 100p 19
XTAL1_LPO GND3
18
XTAL2_LPO GND4
GND5
24
GPIO11 GND6
31
GPIO12 GND7
23
GPIO13 GND8
32
GPIO14 GND9
GND10
39
VDDIORF GND11
38
VDD_IOV GND12
GND13
R648 1 27
POR_DISABLE GND14
2012 40
VREG18 GND15
37
VDD18 PGND
R649 NA
C640
10u
2012
C641 C645
0.1u 0.1u
15
30
50
47
49
48
21
20
C647 22p
2 R656 33p L602
17
22
CN601 L601
16 27nH
MM8430-2600B
1
3
4
5
6
7
8 Bluetooth (BGB202/S2)
9
10
11
12
13
14
51
52
53
- 38 -
33p
FEED NC2
NC1
ANT601