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3. Technical Brief
F. GSM Hardware Subsystem
The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio
together with memory control (MEMSYS) and internal RAM (IRAM).
The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRS
CRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM.
The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge.
The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface.
G. System Control Subsystem
The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and
distributing the clock and reset signals within the ASIC and certain external devices. The GSM core,
GAM and DSP subsystems include their own system controllers that are sourced from SYSCON.
SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slave
peripheral on the slow APB bus under control of the CPU.
The programming of SYSCON controls the fundamental modes of operation within the ASIC.
Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control
registers. SYSCON also controls the requesting protocol through which different subblocks in Ericsson
DB 20000 can request clocks derived from the system clock.
The system controller also stores the chip-ID number in a read only register.
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