LG -A120 Service Manual page 28

- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
- All blocks are protected by VPP=VIL
‧ Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
‧ Erase Suspend/Resume
‧ Program Suspend/Resume
‧ Unlock Bypass Program/Erase
‧ Hardware Reset (RESET)
‧ Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
‧ Endurance : 100,000 Program/Erase Cycles
‧ Support Common Flash Memory Interface
‧ Low Vcc Write Inhibit
<UtRAM2>
• Process technology: CMOS
• Organization: 2M x 16 bit
• Power supply voltage: 1.7V~1.95V
• Three state outputs
• Supports Configuration Register Set
- CRE pin set up
- Software set up
• Supports power saving modes
- PAR (Partial Array Refresh)
- DPD (Deep Power Down)
- Internal TCSR (Temperature Compensated Self Refresh)
• Supports driver strength optimization
• Support 2 operation modes
- Asynchronous mode (4-Page)
- Synchronous mode
• Random access time:70ns
• Page access time:20ns
• Synchronous burst operation
- Max. clock frequency : 104MHz
- Fixed and Variable read latency
- 4 / 8 / 16 / 32 and Continuous burst
- Wrap / No-wrap
- Latency : 3(Variable) @ 104MHz
- Burst stop
- Burst read suspend
- Burst write data masking
28