LG -A120 Service Manual page 17

Dedicated DMA bus
7 DMA channels
320K bits on-chip SRAM
On-chip boot ROM for Factory Flash Programming
Watchdog timer for system crash recovery
3 sets of General Purpose Timer
Circuit Switch Data coprocessor
Division coprocessor
External Memory Interface
Supports up to 2 external devices
Supports 16-bit memory components with maximum size of up to 128M Bytes each
Supports Flash and SRAM/PSRAM with Page Mode or Burst Mode
Industry standard serial LCD Interface
Supports multi-media companion chips with 8/16 bits data width
Flexible I/O voltage of 1.8V ~ 2.8V for memory interface
Configurable driving strength for memory interface
User Interfaces
5-row × 7-column keypad controller with hardware scanner
Supports multiple key presses for gaming
SIM/USIM Controller with hardware T=0/T=1 protocol control
Real Time Clock (RTC) operating with a separate power supply
General Purpose I/Os (GPIOs)
2 Sets of Pulse Width Modulation (PWM) Output
Alerter Output with Enhanced PWM or PDM
6 external interrupt lines
Security
Supports security key and 59 bit chip unique ID
Connectivity
3 UARTs with hardware flow control and speed up to 921600 bps
DAI/PCM and I2S interface for Audio application
Low Power Schemes
Power Down Mode for analog and digital circuits
Processor Sleep Mode
Pause Mode of 32KHz clocking at Standby State
3-channel Auxiliary 10-bit A/D Converter for application usage other than battery monitoring
Power and Supply Management
2.8V to 5.5V Input Range
Charger Input up to 8V
Seven LDOs Optimized for Specific GSM
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