Siemens SXG 75 Service Repair Documentation page 20

6.2.3 Clock distribution
The master clock for Wolf 5 baseband and RF systems runs at 19.2MHz. The clock is generated by
Voltage-Controlled-Temperature-Compensated-Crystal-Oscillator Z1000. The clock is buffered to
VREG_MSMP (2.6V) levels within the PM6650, and then sent to the MSM6250. The PM6650 buffer
is enabled by logic control TCXO_EN from the MSM6250. The MSM6250 integrates a phase-locked
loop and digital dividers to derive internal clocks from the TCXO clock input.
The TCXO is also buffered by D1300 to feed the Bluetooth RF Module, N1600. This buffer is only
enabled when the Bluetooth supply (VREG_AUX2) is active.
A 32.768 kHz clock (SLEEP_CLK) is generated by the PM6650, and fed to the MSM6250. This
clock is used for low-power operation during phone idle periods when the TCXO is disabled. It also
drives a Real-Time-Clock circuit in the PM6650. The power supply for the Sleep Oscillator and
associated Real-Time-Clock is derived from the battery voltage and backup capacitor C1312. This
means the clock is active when the phone is powered off, and for 40 seconds when the battery is
removed.
A 48MHz clock is provided by Z1700. This is used internally by the MSM6250 to control USB
functions.
Block diagram
Technical Documentation
TD_Repair_L3_SXG75_R1.0.pdf
Company Confidential
2006©BenQ
Release 1.0
01/2006
Page 20 of 73