Sony DVP-S7700 Service Manual page 84

(6-9) Reserved Data Head Byte Reading
ROM (IC803) → ARP (IC806) → Decrypt (IC811) reserved data
head byte read matching check
Error 05: Write/read data mismatch error
22: Decrypt (IC811) interruption is not detected
AC-3 audio data stored in ROM (IC803) are transferred to the
Decrypt via ARP (IC806), then the reserved data head bytes are
read from Decrypt (IC811) register.
As this audio data consists of 5 sectors, 0, 1, 2, 3, 4 data are writ-
ten at the head of reserved data of respective sectors.
Whether these data are matched is checked through every sector
interruption.
If write/read mismatch error occurred, checking can be repeated.
(7) AV Decoder (IC203)
(7-2) Register in AV Decoder (IC203)
Register write → Register read matching check
Error 05: Write/read data mismatch error
"0x00" – "0xff" data are written to 51 registers where all bits can
be written/read, then they are read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
(7-3) Reset Line in AV Decoder (IC203)
Register write → Hard reset → Register read matching check
Error 02: Reset error
05: Write/read data mismatch error
After "0xff" is written to the Capture/Compare Control Register
0, whether it is initialized to "0x00" by the reset pulse signal is
checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
(7-4) DREQ Signal Line in AV Decoder (IC203)
AV Decoder (IC203) DMA check
Error 03: Data write error
04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
The connection of DREQ signal line to the AV Decoder (IC203)
is checked through DMA transfer.
If no error is found in DMA transfer, the transferred data are com-
pared with the DRAM (IC810) data read from the register.
(7-5) DRAM in AV Decoder (IC203)
ROM data → AV Decoder (IC203) → DRAM (IC810) → AV De-
coder (IC203) read matching check
Error 03: Data write error
04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
ROM (IC803) patterns are copied to all areas to be checked. Be-
cause of large DRAM (IC810) capacity, each time 256 bytes are
copied, the addresses of copy source (ROM) are returned by 255
bytes. In detail check, to verify all bits in DRAM (IC810), the bit
patterns are checked again after inversion. DMA is used when
writing/reading the data. Though the bus width of AV Decoder
(IC203) is 64 bits, the display is given in 8 bits. Namely, actual
address is 1/8 of displayed data, and lower 3 bits indicate the byte
position.
Overwriting by the shadow can be detected, as the data are written
to all areas, then read. In the detail check, all areas of RAM are
checked twice by inverting the data, while in the simple check one
block is checked, then subsequent 4 blocks are skipped, and also
inverted data are not checked.
If write/read mismatch error occurred, checking can be repeated.
(7-6) Connection from ARP (IC806) to AV Decoder (IC203)
ROM data → ARP (IC806) → Decrypt (IC811) → AV Decoder
(IC203)
Error 04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
10: Chip-to-chip data transfer error
AC-3 audio data stored in ROM (IC803) are written to the ARP
(IC806), then whether they are transferred to the AV Decoder
(IC203) is checked. If transfer error is not detected, the address of
AV Decoder (IC203) to which data are transferred is displayed on
the terminal.
A part of data transferred to the AV Decoder (IC203) is read into
Syscon RAM (IC802) through DMA, and compared with ROM
(IC803) data.
(7-7) Interrupt Line in AV Decoder (IC203)
DRAM data of AV Decoder (IC203) → (DMA COPY) DRAM in
AV Decoder (IC203) another area
Error 31: AV Decoder (IC203) interruption is not detected
Data transfer stop interruption which is generated through
DMA copy of DRAM data in AV Decoder (IC203) to another area
is detected.
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