Ram Configuration - HP 340 Series Service Manual

During a write-to-nlemory operation, the SPU sends a data word to the RAM board along with
the address of a storage location for the data word. During a read-from-memory operation, the
SPU sends the storage location address only, and receives back the data word stored at that
location.
The data word sent to the RAM board is temporarily stored in the Data_In Latch. The data is
also sent to the Check Bit Generator/Checker, which generates the appropriate check bits and
stores them temporarily in the Check_Bit_In Latch.
The RAM boards use dynamic RAM ICs which must be refreshed. This function is accomplished
by the Refresh Controller, which generates refresh requests to the RAM Cycle Controller at the
current refresh request rate.
A RAM Cycle Controller, in combination with the Refresh Controller, is the source of RAM
Row Address Strobe (RAS), Column Address Strobe (CAS) and Write Enable (WE) signals.
These signals are sent on to the Rowand Column Multiplexor.
The Rowand Column Multiplexor logically ands the address from the Arbitration Controller
with RAS and CAS. When the correct storage location is selected, the WE strobe pulse causes
the data word and check bits to be transferred from the In Latches to permanent storage in the
RAM Array.
Each RAM board has thirty-six 1 Mbit by 1 bit dynamic RAMs (DRAM). The excess above
32 DRAMs is required in order to accommodate the data integrity scheme (the Check Bit
Generator/Checker is described above).
When the SPU desires information to be read from the RAM Array, it sends the address
of the appropriate storage location to the RAM board. This address follows the same path
as for writes. When the correct storage location has been selected by the Rowand Column
Multiplexor:1 a strobe pulse causes the contents to be transferred to the Data_Out Register and
the Check_Bits_Out Register. The Check Bits are sent to the Check Bit Generator/Checker
and processed as described above. The data word is sent back to the SPU along the same path
as for incomLing data.
RAM Configuration
All RAM is completely auto-configuring. But it's important to know which one of up to four
RAM boards uses what address block. If a memory error is displayed during self-test, the failing
address can be related to a specific RAM board.
A memory bus from the processor board's RAlVl controller circuits goes to each RAM board
connector. Unlike other Series 300 computers, these connectors are not wired in parallel on the
memory bus. Each RAM board connector is uniquely wired to the RAM addressing circuits for
a specific block of RANI.
RAM blocks are 4Mbytes each. The CPU addresses memory from the top down with the top
hexadecimal address being FFFFFFFF. Address FFFFFFFF is the first, or top address of the
connector labeled RAM 1 closest to the power supply. The first RAM board installed must go
in connector RAM 1, the second in connector RAM 2, and so on.
Functional Description
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