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IC description
(4) Pin Description
Pin 1 - STANDBY Input
Via this input pin, the standby mode of the CIP 3250A is
enabled. A high level voltage switches all outputs to
tristate mode, and power consumption is signigicantly
reduced. When the IC IS returned to active mode, a reset
is generated internally. Connect to VSS if not used.
Pins 2 to 9 - B7 to B0 Blue Output
In a stand alone application, where the CIP 3250A serces
as an A/D-converter, these are the output for the digital
Blue signal (pure binary) or the digital U signal (2’s com-
plement). Leave vacant if not used.
Pin 10 to 17 - GL7 to GL0 Green/Luma Output
At these outputs, the digital luminance signal is received in
pure binary cided format for DIGIT 2000 and DIGIT 3000
applications. In a stand alone application, where the CIP
3250A serves as an A/D-converter, these are the outputs
for the digital Green signal(pure binary) or the digital luma
signal(pure binary). Leave vacant if not used.
Pin 18 - PVSS Output Pin Ground
This is the common ground connection of all output stages
and must be connected to ground.
Note : All ground pins of the chip (i.e.
18,52,58,60,62,64,66 and 68) must be connected together
low resistive. The layout of the PCB must take into consid-
eration the need for a low-noise ground.
Pin 19 - PVDD Output Pin Supply + 5V/+3.3V
This pin supplies all output stages and must be connected
to a positive supply voltage.
Note : The layout of the PCB must take into consideration
the need for a low-noise supply. A bypass capacitor has to
be connected between ground and PVDD
Pins 20 to 27 - RC7 to RC0 Red/Chroma Output
These are the outputs for the digital chroma signal in the
DIGIT 3000 system, where U and V are multiplexed byte-
wise. In a DIGIT 2000 system, RC3 to RC0 and RC7 to
RC4 carry the halfbyte(nibble) multiplex format. In a stand
alone application, where the CIP 3250A serces as an AD-
converter, these are the outputs for the digital Red sig-
nal(pure binary) or the digital chroma V signal (2 ’s compo-
nent). Leave vacant if not used.
Pin 29 - AVI Active Video Input
In a DIGIT 2000 application, this input can be connected
to ground. In a DIGIT 3000 application, this input expects
the DIGIT 3000 AVI signal. In a stand alone application,
this input expects the VSYNC vertical sync pulse. Connect
ground if not used.
Pin 30 - FSY Front Sync Input
In a DIGIT 2000 application, this input pin expects the
DIGIT 2000 SKEW protocol. In a DIGIT 3000 application,
this input expects the DIGIT 3000 FSY protocol. In a stand
alone application, this unput expects the HSYNC horizon-
tal sync pulse. Connect to ground if not used.
Pin 31 to 32 - SDA and SCL of
These pins connect to the
control of the CIP 3250A via the internal registers. The
SDA pin is the data input/output, and the SCL pin is the
clock input/output of
are writerable(except address hex27) and readable.
Pin 33 to 35 - PRIO0 to PRIO2 Priority Bus
These pins connect to the Priority Bus of a DIGIT 3000
application. The Picture Bus Priority lines carry the digital
priority selection signals. The priority interface allows digi-
tal switching of up to 8 sources to the backend processor.
Switching for different sources is prioritized and can be on
a per pixel basis. In all other applications, they must not be
connected.
Pin 36 to 43 - C0 to C7 Chroma Input
These are the inputs for the digital chroma signal which
can be received in binary offset or 2 ’s complement coded
format. In a DIGIT 2000(4:1:1) system, C3 to C0 take the
halfbyte (nibble) multiplex format. C7 to C4 have to be
connected to ground. Within the DIGIT 3000(4:2:2) sys-
tem, U and V are multiplexed bytewise. Connect to ground
if not used.
17
2
-Bus
I C
2
I C
bus, which takes over the
2
I C
bus control interface. All registers
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