Pll Frequency Synthesizer For Electron Alignment - JVC MX-GT700 Service Manual

MX-GT700
LC72131(IC02) : PLL frequency synthesizer for electron alignment
1. Pin layout
1
20
XIN
2
19
CE
3
18
DI
4
17
CL
5
16
DO
6
15
BO1
7
14
BO2
8
13
BO3
9
12
BO4
10
11
I01
3.Pin function
Symbol
Pin No.
XIN
1
XOUT
20
FMIN 14
AMIN
13
CE
2
1-32
2. Block diagram
XOUT
VSS
1
AOUT
AIN 20
PD
VDD
14
FMIN
AMIN
I02
IFIN
13
2
3
4
5
15
19
Type
Crystal resonator connection
Xtal OSC
(4.5MHz/7.2MHz)
Serial data input : FMIN is selected when DVS is set to 1.
The input frequency range is from 10 to 160MHz.
Local
The signal is passed through a built-in divide-by-two prescaler
oscillator
and then supplied to the swallow counter.
signal input
A1 though the range of divisor setting is from
272 to 65, 535, the actual divisor is twice the setting since
there is also a built-in divide-by-two prescaler.
Serial data input : AMIN is selected when DVS is set to 0.
Local
Serial data input : When SNS is set to 1 :
oscillator
The input frequency range is form 2 to 40MHz
signal input
The signal is supplied directly to the swallow counter.
The range of divisor setting is from 272 to
65, 535 and the actual divisor will be the value set.
Serial data input : When SNS is set to 0 :
The input frequency ranges is from 0.5 to 10MHz.
The signal is supplied directly to a 12-bit
programmable divider.
The range of divisor setting is from 4 to 4,095 and the
actual divisor will be the value set.
Most be set high when serial data is input to the
Chip enable
LC72131M (DI ), or when serial data is output (DO).
Reference
Driver
Swallow
1
Counter
2
1/16,1/17 4bits
12bits
Programmable
Divider
CCB
Data Shift Register & Latch
I/F
Power
on
Reset
6 7 8
Functions
Phase
Detector
Charge
Pump
Unlock
Detector
Universal
Counter
9 10 12
Circuit configuration
16
17
18
11
(1/2)
S