Components - N1400, N1410; Components - N14111, N1412 - Sony Ericsson W995 Troubleshooting Manual

N1400 A-GPS 1200-0700
Multiplexed Core System
Serial Interface Supply Integration
VDD_CORE
OMS2
OMS1
OMS0
SYNC
CNTIN VDD_CORE
CLK nRESET
Hammerhead II
(SG-UFWLB-49 )
VDD_PLL VDD_RFREG_IN
VDD_LP_PLLREG_IN VDD_RF
VDD_LPREG_OUT
VDD_LP
VDD_IO
JTAG Interface Decouple VCO Mixer EXT_LNA
Pin Pin Pad Pad O/P
No. Name Type Usage State
Pad Functional Description
A1 HIF3 I/O Host Interface
I - - -
UART_RXD / OMS[2:0]=[1,1,1]: UART Interface: Data Input
(I) - - -
UART_RXD / OMS[2:0]=[1,1,0]: UART Interface: Data Input (Ignored)
I - - -
2
I C_GROUP1 / OMS[2:0]=[1,0,1]: Selection of I 2 C group address
I - - -
SPI_nSCS OMS[2:0]=[1,0,0]: SPI chip select
A2 HIF4 I/O Host Interface
O - 0 0
UART_nRTS / OMS[2:0]=[1,1,1]: UART Interface: hardware flow control
Z - Z Z
UART_nRTS / OMS[2:0]=[1,1,0]: UART Interface: hardware flow control
I - - -
2
I C_A0 / (Tristated)
I - - -
SPI_SI OMS[2:0]=[1,0,1]: Selection of I 2 C group address bit 0
OMS[2:0]=[1,0,0]: SPI serial data input
A3 CNTIN I I - - - Digital high accuracy frequency reference
A4 CLK I / AI I - - - Clock signal input. Selectable as digital or analog input
A5 VDD_PLL PI/ - - - - Digital PLL supply Decoupling
PO
A6 VDD_LP_PLLREG_I PI - - - - PLL voltage and Low Power core regulator input
N
A7 VDD_IO PI - - - - Digital I/O supply
B1 VSS_DIG GND - - - -
B2 HIF2 I/O Host Interface
UART_TXD / O - 0 0 OMS[2:0]=[1,1,1]: UART Interface: Data Output
Z - Z Z
UART_TXD / OMS[2:0]=[1,1,0]: UART Interface: Data Output (Tristated)
I - - -
2
I C_GROUP0 / OMS[2:0]=[1,0,1]: Selection of I 2 C group address
I - - -
SPI_SCK OMS[2:0]=[1,0,0]: SPI clock
B3 HIF5 I/O - - - - Host Interface
UART_nCTS / I - - - OMS[2:0]=[1,1,1]: UART Interface: hardware flow control
(I) - - -
UART_nCTS / OMS[2:0]=[1,1,0]: UART Interface: hardware flow control
I - - -
- / (Ignored)
O / Z - Z Z
SPI_SO OMS[2:0]=[1,0,1]: not used (tie to "0")
OMS[2:0]=[1,0,0]: SPI serial data output
B4 VDD_LPREG_OUT PO - - - - Low Power core regulator output
B5 TDI I / O I PU "C" 1 1 Serial Data Input (JTAG, IEEE 1149.1)
B6 VDD_LP PI - - - - Low Power supply
PI - - - -
B7 VDD_CORE Digital core supply
C1 VDD_COREREG_O PO - - - - Digital core voltage regulator output
UT
C2 VDD_IO PI - - - - Digital I/O supply
P a d T y p e D e c s i r t p o i n C o m m e n s t
GND Chip Ground All signals are referred to this
P I Power In Supply to a voltage domain
P O Power Out Regulator Output
P I/O Power Out Supply to a voltage domain and regulator Output
I /O Digital Signal All Digital Pads are I /O Pads which are configured internally as required.
Pad - All are configured as Push-Pull e xcept those marked as OD (open drain)
- All have hysteresis by default, but is onl y mentioned when it is required for correct
system operation.
A I Analog Input
A O Analog Output
AI/O Analog Input/ Bidirectional analog pad.
Output
PU Internal Pull Up
PD Internal Pull
Down
APPENDIX
Top view (PCB footprint)
A7 B7 C7 D7 E7 F7 G7
A6 B6 C6 D6 E6 F6 G6
A5 B5 C5 D5 E5 F5 G5
A4 B4 C4 D4 E4 F4 G4
A3 B3 C3 D3 E3 F3 G3
A2 B2 C2 D2 E2 F2 G2
A1 B1 C1 D1 E1 F1 G1
0.3 0.25
mm mm
0.4 mm
3.7 mm
C3 HIF0 I/O Host Interface
I - - -
- / OMS[2:0]=[1,1,1]: not used (tie to "0")
I - - -
- / OMS[2:0]=[1,1,0]: not used (tie to "0")
2
I C I - - -
I 2 C_SCL / OMS[2:0]=[1,0,1]: I 2 C clock
I - - -
- OMS[2:0]=[1,0,0]: not used (tie to "0")
C4 HIF1 I/O Host Interface
I - - -
- / OMS[2:0]=[1,1,1]: not used (tie to "0")
I - - -
- / OMS[2:0]=[1,1,0]: not used (tie to "0")
2
I C I/ O OD Z Z
I 2 C_SDA / OMS[2:0]=[1,0,1]: I 2 C data
I - - -
- OMS[2:0]=[1,0,0]: not used (tie to "0")
C5 TDO I / O O - Z Z Serial Data Output (JTAG, IEEE 1149.1)
C6 TCK I / O I PD "C" 0 0 Clock (JTAG, IEEE 1149.1)
C7 nTRST I / O I PD "A" 0 0 Reset Input (JTAG, IEEE 1149.1)
D1 VDD_COREREG_IN PI - - - - Digital core voltage regulator supply
D2 VSS_DIG GND - - - -
D3 OMS1 I / O I - - - Operational mode select / Bus interface select
D4 SYNC I I - - - Digital reference time pulse
D5 VSS_DIG GND - - - -
D6 TMS I / O I PU "C" 1 1 State Machine Control Signal (JTAG, IEEE 1149.1)
D7 VSS_DIG GND - - - -
E1 RTCCLK I / O I Hyst - - 32.768kHz clock signal input
E2 POWERON I / O I - 0 0 Power On signal to chip
E3 OMS0 I / O I - - - Operational mode select / Bus interface select
E4 VSS_LNA GND - - - -
E5 VSS_RF GND - - - -
E6 MIX_IN_PLUS AI AI - - - Differential mixer input
E7 VDD_CAP PI/O PI/O - (Z) (Z) RF Digital Supply Decoupling
F1 nINTR I / O O OD Z Z Interrupt request signal to host
F2 RX_HOLD I / O I - - - RX_HOLD signal (From host to indicate that the host is
transmitting)
F3 nRESET I / O I Hyst 0 1 Chip reset signal
F4 VDD_RFREG_IN RF voltage regulator input
PI - - - -
F5 EXT_LNA_CTRL0 AI/O O - - - External LNA control
F6 MIX_IN_MINUS AI AI - - - Differential mixer input
F7 VDD_VCO PI/O PI/O - (Z) (Z) Buffer capacito r for VCO supply
G1 VDD_CORE PI - - - - Digital core supply
G2 OMS2 I / O I - - - Operational mode select
G3 VDD_CORE PI - - - - Digital core supply
G4 VSS_RF GND - - - -
G5 VDD_RF PI/0 - - - - RF Analog Supply Decoupling
G6 VSS AI AI - - -
G7 N.C. AO AO - - - This ball should be left unconnected
Components - N1400, N1410, N1411, N1412
N1410 IC Amp MicroDFN-6 1215-1892
+
GND 1
GND 2
RFIN 3
BIAS
N1411 IC Vreg CS-5 1200-3994
Dimensions in mm and tolerance 0.1 mm unless noted.
1,052
0,952
1,416
1,316
Pin A1 Index Area
0,30
0,20
N1412 IC Vreg PLP1010-4 1201-1568
VDD CE
3
4
TOP VIEW
2
1
VOUT GND
Pin No. Symbol
1 V
OUT
2 G ND
3 CE
4 V
DD
T ab is G ND le vel. ( T hey are c onnec ted to the r evers e s ide of this IC.)
SEMC Troubleshooting Manual
6 RFOUT
5 SHDN
4 V
CC
CS-5 PACKAGE
(TOP VIEW)
0,35
0,25
C3 C1
IN OUT
B2
GND
A3 A1
NR EN
CE VDD
3
4
BOTTOM VIEW
2
1
GND VOUT
Description
Output Pi n
G round Pi n
Ch ip E nable P in ("H" A ctive)
Input P in
1230-1858 rev. 1
W995
107 (125)