Main(Reg) Schematic Diagram - JVC GZ-MG555US Schematic Diagrams

MAIN(REG) SCHEMATIC DIAGRAM

TO MAIN IF
BATT+
!
F6002
NMFZ007-2R5X-K
GND
TO MAIN IF
ADP_DC
(CN108)
R6009
OPEN
J601
QNA0040-001
3 !
F6001
NMFZ007-2R5X-K
4
2
C6009
0.1
5
1
R6010
OPEN
C6010 D6002
0.1 MA8068-X
TO CPU,MAIN IF
ADP_L
(CN108)
TO MAIN IF BATT_CHK
R6011
82k
V_BATT
C6011
R6012 OPEN
33k
TO CPU
R6021
150k
UNREGCHK
C6013
R6022 OPEN
39k
0 1 MAIN(REG)
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
IC6003
OPEN
VI SEN
GND G
CTL ST
R6019
0Ω
D2 G2
D2 S2
R6001
D1 G1 0Ω
R6020
D1 S1 0Ω
L6002
L6001
OPEN
OPEN
Q6001
SP8J5-X
D6001
OPEN R6002
0Ω
C6001
OPEN
R6013
0Ω
IC6001
FA7736F
GND
VCH9
C6002
4.7
VCC0
C6003
C6902 1
3900p VREG
R6902
1k FB9
C6901 R6901
1000p 4.7k
OPEN
IN9-
R6504
C6501 R6501
0.1 680
R6505
R6503
3.3k
47k FB5
C6502 R6502
0.033 6.8k
IN5-
R6203 R6204
15k 18k FB2
IC6001
C6201 R6201
R6205
220p 8.2k
OPEN
IN2-
R6202
C6202 C6301 R6301 FA7736F
0Ω
1000p 220p 8.2k
R6304
R6303
47k FB3
11k
C6302 R6302
1500p 0Ω
IN3-
C6401 R6401
R6403 R6404 220p 8.2k
R6405
30k 15k 0Ω FB4
C6402 R6402
1000p
0Ω
IN4-
C6101 R6101
R6103 R6107 R6104 220p 3.3k
18k 1k 10k
FB1
IN1-
R6102
C6102
0Ω R6004
1500p
47k
RDT
C6103
1
C6403
1
C6104
10
(No.YF183)2-17
R6701
OPEN
C6701
4700p
DATA
CLK
CS
C6007
OPEN
RST
C6006
0.1
OUT7S
OUT6S
OUT6P
C6005
1
VCC6
VCC2
C6004
OPEN
OUT2N
OUT2P
PGND5
D6901 L6901
RB551V-30-X NQL79GM-470X
OUT9
47µ
F6003
0Ω
VCC9
C6903
4.7
VCC5
C6503 C6504
1
1
2
OUT5
! 3
F6501
NMFZ007-R63X-K
L6501
220µ
NQL52EM-221X
C6303
1
C6404 C6304
10 10
C6505 4
1
1
2-18(No.YF183)
IC6002
R6017
OPEN OPEN
DET
VSS OUT
R6016
OPEN
C6012
OPEN
L6701
Q6701 NQL52EM-470X Q6702
R6716
RSR025P03-X 47µ RSR025P03-X
0.2
D6702
NRV142F-R20X
RB160M-30-X
Q6703
RSR025P03-X
C6704
1
C6708 C6705
10 10
R6715 R6714
1M 1M
Q6201 L6201
RSR025P03-X 68µ NQL52EM-680X
C6203
1
C6204
10
D
Q6202
RSR025N03-X
G
S
D6902
OPEN
L6502 R6903
D6501
10µ R6520 0Ω
RB481K-X
0Ω
1
NQL38DK-100X
4
Q6504
R6513
OPEN
Q6503
OPEN
3 6
5 2
C6506
1 4 1
Q6505
EMX1-W C6512
1
C6510
R6512
1
OPEN
C6508
R6510
OPEN C6509
10k
1
Q6506 R6527
OPEN
1 4
3 6
2 5
C6507
Q6502 6 3 5
1
UMT1N-W
2
4 1
Q6507
D6502 R6509 EMX1-W
RB481K-X 33k
C6513 C6514
3
4.7 1
R6526
8.2k
2
R6511
0Ω
yf183_y10690001a_rev0.1
DC_CHECK
CHRG_EVR
I_MTR
R6005
1k
TO MAIN IF(CN110),
REGRTC_OUT
R6006 1k
REGRTC_CLK CPU
R6007 1k
REG_CS
R6008 1k
SYS_RSTL
REG_4.9V
REG_1.8V
TO MAIN IF,CPU,DSP
AL_3.1V
BL_POWER TO MAIN IF
REG+CCD TO MAIN IF(CN105)
REG_LCD
TO MAIN IF(CN105)
REG-CCD
REG_1.2V
TO MAIN IF
DRV_3.3V
TO MAIN IF(CN101,105)
CAM_3.1V
REG_3.1V