Gate Array Theory Of Operation; Cpu Theory Of Operation; Introduction; Resetcircuit - Radio Shack TRS-80 Service Manual

4P GATE ARRAY THEORY OF OPERATION
5.2.4.1 Video Timing
'This is the state to be written to latch U85. Signal is inverted
before being input to U ; 48.
fed to the CPU U45. PClK is generated as a symmetrical
clock and is never allowed to be short cycled. (eg.) Not al-
lowed to generate a low or high pulse under 110
nanoseconds.
MOOSEl and 8064' signals are used to select the desired
video mode. 8064' controls which reference clock is used by
U127 and MOOSEl controls the single or double character
width mode. Refer to the foilowing chart for selecting each
video mode.
Video Mode
64 x 16
32 x 16
80
x
24
40x24
MOOSEl
o
1
o
1
8064'
o
o
1
1
The video timing is also generated by U148 with the help of a
Pll Multiplier Module (PMM) U146. These two iCs generate all
the necessary timing signals for the four video modes: 64 x 16,
32 x 16, 80 x 24, and 40 x 24. Two reference clocks are required
for the four video modes. One reference clock is 10.1376 MHz.
It is generated internally to U148, and is used by the 64 x 16 and
32 x 16 modes. The second reference clock is a 12.672 MHz
(12M) clock which is generated by the PMM U146. 12M clock
is used by the 80 x 24 and 40 x 24 modes. A 1.2672 MHz
(1.2M16) signal is output from pin 3 of U148 and is generated
from the master reference clock, the 20.2752 MHz crystaL
1.2M16 is used for a reference clock for the PMM. The PMM is
internally set to oscillate at 12.672 MHz which is output as 12M.
U148 divides 12M by 10 to generate a second 1.2672 MHz
clock (1.2M10) which is fed into pin 5 of U146 (PMM). The two
1.2672 MHz signals are internally compared in the PMM where
it corrects the 12.672 MHz output so it is synchronized with the
20.2752 MHz clock.
5.2.1 Introduction
5.2.4 System Timing
5.2.3 CPU
Contained in the following paragraphs is a description of the
component parts of the Model 4P CPU Gate Array. It is divided
into the ioglcal operational functions of the computer. All com-
ponents are located on the Main CPU board inside the case
housing. Refer to Section 3 for disassembly/assembly
procedures.
5.2 CPU THEORY OF OPERATION
The Modei 4P reset circuit provides the neccessary reset
pulses to all circuits during power up and reset operations. R25
and C214 provide a time constant which holds the input of U121
low during power-up. This allows power to be stable to all cir-
cuits before the RESEr and RESET signals are applied. When
C214 charges to a logic high, the output of U121 triggers the
input of a retriggerable one-shot multivibrator (U1). U1 outputs
a pulse with an approximate width of 70 microsecs. When the
reset switch is pressed on the front panel, this discharges C214
and holds the input of U121 low until the switch is released. On
reiease of the switch, C214 again charges up, triggering U121
and U1 to reset the microcomputer. Another signal POWRSr
is generated to clear drive select circuit immediately when
reset switch is pressed.
5.2.2 Reset Circuit
The central processing unit (CPU) of the Model 4P microcom-
puter is a Z80A microprocessor. The Z80A is capable of run-
ning in either 2 MHz or 4 MHz mode. The CPU controls all
functions of the microcomputer through use of its address lines
(AO-A15), data lines (00-07), and control lines (/M1, /IOREQ,
/RO, IWR, /MREQ, and /RFSH). The address lines (AO-A15)
are buffered to other ICs through two 74lS244s (U67 and U27)
which are enabled all the time with their enables pulled to GNO.
The control lines are buffered to other ICs through a 74F04
(U87). The data lines (00-07) are buffered through a bi-direc-
lional 74lS245 (U86) which is enabled by BUSEN' and the di-
rection is controlled by BUSOIW.
The main timing reference of the microcomputer, with the
exception of the FOC circuit, is generated by a Gate Array
U148 and a 20.2752 MHz CrystaL This reference is inter-
nally divided in the Gate Array to generate ail necessary tim-
ing for the CPU, video circuit, and RS-232-C circuit. The
CPU ciock is generated U148 which can be either 2 or
4MHz depending on the logic state of FAST input (pin 6 of
U148). If FAST is a logic low, the U148 generates a 2.02752
MHz clock. If FAST is a logic high, U148 generates a
4.05504 MHz signal. PClK (pin 23 of U148) is filtered
through a ferrite bead (FB2) and 22fl Resistor (R9) and then
85