Ram - Radio Shack TRS-80 Service Manual

File Loader (RST 28H)
There are several pieces of information left in memory by the
boot ROM which are useful to system programmers. These are
shown below:
Accepts None
Returns
Z
NZ
Errors
o
RAM
Location
401DH
4055H
4056H
4057H
4059H
405BH
405CH
Success
Failure, error code in A
Any errors from the disk I/O call of the
byte fetch call and:
The ROM image was not found on drive 0
Description
ROM Image Selected (% for none
selected or A-G)
Boot type
1 ~ Floppy
2 ~ Hard disk
3 ~ ARCNET
4 ~ RS-232C
5 - 7
~
Reserved
Boot Sector Size (1 for 256,2 for 512)
RS-232 Baud Rate (only valid on RS-
232 boot)
Function Key Selected
o
~
No function key selected
<Fl> or <1> 86
<F2> or <2> 87
<F3> or <3> 88
<Caps> 85
<Ctrl> 84
<Left-Shift> 82
<Right-Shift> 83
Reserved 80-81 and 89-90
Break Key Indication (non-zero if
<Break> pressed)
Disk type (0 for LDOS/
TRSDOS 6,1 for
TRSDOS l.x)
The DRAMs require multiplexed incoming address lines. This
is accomplished by ICs U111 and U112 which are 74LS 157
multiplexers. Data to and from the DRAMs are buffered by a
74LS245 (UI17) which is controlled by Page Map PAL,
un
O.
The proper timing signals RASO', RAS1', MUX', and CAS' are
generated by a delay line circuit U97. U115 (1/2 of a 74S112)
and U116 (1/4 of a 74F08) are used the generate a precharge
circuit. During Ml cycles of the Z80A in 4 MHz mode, the high
time in MREQ has a minimum time of 110 nanosecs. The spec-
ification of 6665 DRAM requires a minimum of 120 nanosecs so
this circuit will shorten the MREQ signal during the Ml cycle.
The resulting signal PMREQ is used to slart a RAM memory
cycle through U113 (a 74S64). Each different cycle is controlled
at U113 to maintain a fast Ml cycle so no wait states are re-
quired. The output of U113 (PRAS') is ANDed with RFSH to not
allow MUX' and CAS' to be generated during a REFRESH
cycle. PRAS' aiso generates either RASO' or RAS1', depend-
ing on which bank of RAM the CPU is selecting. GCAS' gen-
erated by the delay line U97 is latched by U115 (1/2 of a
74S112) and held to the end of the memory cycle. The output
of U115 is ANDed with VIDEO signal fa disable the CAS' signal
from occurring if the cycle is a video memory access. Refer to
Ml Cycle Timing (Figure 5-8. and 5-9.), Memory Read and
Memory Write Cycle Timing (Figure 5-10.) and (Figure 5-11.).
Keep in mind that Model III ROM image will initialize these
areas, so this information is useful only to the Model 4 mode
programmer.
5.1.7 RAM
Two configurations of Random Access Memory (RAM) are
available on the Model 4P: 64K and 128K. The 64K and 128K
option use the 6665-type 64K xl 200NS Dynamic RAM, which
requires only a single
+
5v supply voltage.
37