Graphics Port - Radio Shack TRS-80 Service Manual

5.1.12 Graphics Port
The Graphics Port (J7) on the Model 4P is provided to attach
the optional Graphics Board. The port provides 00-07 (Data
Lines), AO-A3 (Address Lines), IN', GEN' and RESET' for the
necessary interiace signals for the Graphics Board. GEN· is
generated by negative ORing Port selects GSELO' (8C-8FH)
and GSEll' (80-83H) together by (1/4 of 74LS08) U23. The re-
sulting signal is negative AN Oed with 10RO' by (1/4 of 74S32)
U62. Seven timing signals are provided to allow synchroniza-
tion of Main Logic Board Video and Graphics Board Video.
These timing signals are VSYNC, HSYNC, DISPEN, DCLK, H,
I, and J. Three control signals from the Graphics Board are
used to sync to CPU access and select different video modes.
WAIT' controls the CPU access by causing the CPU to WAIT till
video is in retrace area before allowing any writes or reads to
Graphics Board RAM. ENGRAF is asserted when Graphics
video is displayed. ENGRAF also disables inverse video mode
on Main Logic Board Video. CL166' (Clear 74L 166) is used to
enable or disable mixing of Main Logic Board Video and Graph-
ics Board Video. If CL166' is negated high, then mixing is al-
lowed in all for video modes 80 x 24, 40 x 24, 64 x 16, and 32 x
16. If CL166' is asserted low, this will clear the video shilt reg-
ister U63, which allows no video from the Main Logic Board. In
this state 8064* is automatically asserted low to put screen in
80 x 24 video mode. Refer to Figure 5-16. Graphic Board Video
Timing for timing relationships. Refer to the Model4/4P Graph-
ics Board Service information for service or technical
jnforma~
tion on the Graphics Board.
5.1.13 Sound
The sound circuit in the Model4P is compatible with the Sound
Board which was optional in the Model 4. Sound is generated
by alternately selling and clearing data bif DO during an OUT to
port 90H. The stafe of DO is latched by U130 (1/2 of a 74LS74)
and the output is amplified by 02 which drives a piezoelectric
sound transducer. The speed of the software loop determines
the frequency, and thus, the pitch of the resulting tone. Since
the Model 4P does not have a cassette circuit, some existing
software that used the cassette output for sound would have
been lost. The Model 4P routes the cassette latch to the sound
board through U142. When the CASSMOTORON signal is a
logic low, the cassette motor is off, then the cassette output is
sent to the sound circuit.
5.1.141/0 Bus Port
The Model 4P Bus is designed to allow easy and convenient in-
tertacing of I/O devices to the Model 4P. The I/O Bus supports
all the signals necessary to implement a device compatible with
the Z80s I/O structure.
57
Addresses:
AO to A7 allow selection of up to 256' input and 256 output
devices if external I/O is enabled.
'Ports 80H to OFFH are reserved for System use.
Data:
DBO to DB7 allow transfer of 8-bit data onto the processor
data bus is external I/O is enabled.
Control Lines:
1. Ml' - Z80A signal specifying an M1 or Operation Code
Fetch Cycle or with 10REO', it specifies an Interrupt
acknowledge.
2. IN' - Z80A signal specifying than an input is in progress.
Logic AND of 10REO' and WR'.
3. OUT' - Z80A signal specifying that an output
IS
in prog-
ress. Logic AND of 10REO' and WR'.
4. lOR EO' - Z80A signal specifying that an input or output
is in progress or
with M1*, it
specifies an interrupt
acknowledge.
5. RESET' - system reset signal.
6. 10BUSINT' - input to the CPU signaling an interrupt from
an I/O Bus device if I/O Bus interrupts are enabled.
7. 10BUSWAIT' - input to the CPU wait line allowing I/O Bus
device to force wait states on the Z80 if external I/O is
enabled.
8. EXTIOSEL' - input to I/O Bus Port circuit which switches
the I/O Bus data bus transceiver and allows and INPUT in-
struction to read 110 Bus data.
The address line, data line, and all control lines except RESET'
are enabled only when the ENEXIO bit in port EC is set to one.
To enable I/O interrupts, the ENIOBUSINT bit in the PORT EO
(output port) must be a one. However, even if it is disabled from
generating interrupts, the status of the 10BUSINT' line can still
read. on the appropriate bit of CPU 10PORT EO (input port).
See Model4P Port Bit assignments for port OFF, OEC, and OEO.