Pioneer SX-SW404 Service Manual page 70

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QQ
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Pin Function
No. Pin Name
A
1 VRA_PLL
2 PLL_FLT_RET
3 PLL_FLTM
4 PLL_FLTP
5 AVSS
6 AVSS
7 VRD_PLL
8 AVSS_PLL
9 AVDD_PLL
10 VBGAP
B
11 RESET
12 HP_SEL
13 PDN
14 MUTE
15 DVDD
16 DVSS
17 VR_DPLL
18 OSC_CAP
19 XTL_OUT
20 XTL_IN
C
21 RESERVED
22 RESERVED
23 RESERVED
24 SDA
TE
L 13942296513
25 SCL
26 LRCLK
27 SCLK
28 SDIN4
29 SDIN3
30 SDIN2
D
31 SDIN1
32 PSVC
33 VR_DIG
34 DVSS
35 DVSS
36 DVDD
37 BKND_ERR
38 DVSS
39 VALID
40 PWM_M_1
E
41 PWM_P_1
42 PWM_M_2
43 PWM_P_2
44 PWM_M_3
45 PWM_P_3
46 PWM_M_4
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47 PWM_P_4
48 VR_PWM
49 PWM_M_7
50 PWM_P_7
F
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I/O
−
Voltage reference for PLL analog supply 1.8V
AO PLL external filter return
AO PLL negative input
AI PLL positive input
P Analog ground
P Analog ground
P Voltage reference for PLL digital supply 1.8V
P Analog ground for PLL
P 3.3V analog power supply for PLL
P Band gap voltage reference
DI System reset input, active low
DI Headphone input/output selector
DI Power down, active low
DI Soft mute of outputs, active low
P Digital power supply 3.3V supply for digital core and most of I/O buffers
P Digital ground for digital core and most of I/O buffers
P Voltage reference for digital PLL supply 1.8V
AO Oscillator capacitor
AO XTL_OUT and XTL_IN are the only LVCMOS terminals on the device
AI XTL_OUT and XTL_IN are the only LVCMOS terminals on the device
−
Connect to digital ground
−
Connect to digital ground
−
Connect to digital ground
2
DIO I C serial control data interface input/output
2
DI I C serial control clock input/output
DI Serial audio data left/right clock (sampling rate clock)
DI Serial audio data clock (shift clock)
DI Serial audio data 4 input is one of the serial data input ports
DI Serial audio data 3 input is one of the serial data input ports
DI Serial audio data 2 input is one of the serial data input ports
DI Serial audio data 1 input is one of the serial data input ports
O Power supply volume control PWM output
P Voltage reference for digital core supply 1.8V
P Digital ground
P Digital ground
P 3.3V digital power supply
Active low. A backend error sequence is generated by applying logic low to this terminal
DI
P Digital ground
DO Output indicating validity of PWM outputs active high
DO PWM 1 output (differential –)
DO PWM 1 output (differential +)
DO PWM 2 output (differential –)
DO PWM 2 output (differential +)
DO PWM 3 output (differential –)
DO PWM 3 output (differential +)
DO PWM 4 output (differential –)
DO PWM 4 output (differential +)
P Voltage reference for digital PWM core supply 1.8V
x ao
y
DO PWM 7 (Line out L) output (differential –)
. DO i PWM 7 (Line out L) output (differential +)
SX-SW404
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8
Pin Function
Q Q
3 6 7 1 3
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3
4
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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4
9 9
2 8 9 9