Denon S-101 Service Manual page 34

QQ
3 7 63 1515 0
QT240 (IC306: 1U-3681)
SNS2
1
SNS2K
2
SNS1
3
SNS1K
4
QT240
OUT1
5
20-SSOP
OUT2
6
OUT3
7
VSS
8
SS/SYNC
9
n.c.
10
SN74LV244APW (IC708, 719: 1U-3694)
SN74HCT244APW (IC205: 1U-3694)
1
OE
2
I0
3
O4
4
I1
5
O5
6
I2
TE
L 13942296513
7
O6
8
I3
9
O7
10
GND
NJM2595 (IC507, 508: 1U-3695)
16
1
SN74LV157APW (IC704: 1U-3694)
SE LECT 1
SEL
1A
2
3
1B
www
1Y 4
5 5
2A
2B 6
7
2Y
.
8
GND
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T
ABLE
Pin
1
2
SNS3K
20
3
SNS3
19
4
5
SNS4K
18
6
SNS4
7
17
8
n.c.
16
9
10
OSC
15
11
VDD
14
12
13
/RES
13
14
OUT4
12 15
16
11 n.c.
17
18
19
20
20
VCC
19
OE2
18
O0
17
I4
16
O1
15
I5
14
O2
13
I6
12
O3
11
I7
9
8
16
Vcc
15
ST
14
4A
13
4B
12
4Y
x ao
y
11 3A
10
3B
i
9 3Y
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8
1-1 P L - QT240-ISS
IN ISTING
Name Description
SNS2 Sense pin (to Rs2 + Cs2)
SNS2K Sense pin (to Cs2, electrode)
SNS1 Sense pin (to Rs1 + Cs1)
SNS1K Sense pin (to Cs1, electrode); speed option
OUT1 Output, key 1
OUT2 Output, key 2
OUT3 Output, key 3
VSS Ground
SYNC/SS Sync in and/or spread spectrum drive
n.c. Unbonded internally
n.c. Unbonded internally
OUT4 Output, key 4
/RES Reset pin, active low. Can usually tie to Vdd.
VDD Power: +4.0 to +5V locally regulated
OSC Oscillator bias in
VSS Ground or no connect
SNS4 Sense pin (to Rs4 + Cs4)
SNS4K Sense pin (to Cs4, electrode); OPT2
SNS3 Sense pin (to Rs3 + Cs3)
SNS3K Sense pin (to Cs3, electrode); OPT1
BU2090F (IC303: 1U-3681)
(IC304, 504: 1U-3695)
VSS 1
DATA 2
CLOCK 3
LCK
4
Q0 5
Q1 6
Q Q
Q2 7
3 6 7 1 3
Q3 8
9
Q4
SN74LVC139APWR (IC902: 1U-3694)
1 16
1G V
C C
2 15 2G
1A
1B 3 14 2A
1Y 0 4 13 2B
u163
5 12 2Y 0
1Y 1
1Y 2 6 11 2Y 1
.
1Y 3 7 10 2Y 2
2Y 3
G ND 8 9
34
2 9 9 4 2 8
18
CONTROL CIRCUIT VDD
17 OE
12-bit SHIFT REGISTER
16 Q11
15 Q10
12-bit STRAGEREGISTER
Q9
14
O U T P U TB U FFE R(O P E ND R A IN )
13 Q8
12
1 5 0 5 8 2 9 Q7 9 4
Q6
11
Q5
10
F UNC T ION TAB LE
(each decoder/demultiplexer)
INP UT S
S E LE C T m
G G
B A Y 3
L L L H
co
L L H H
L H L H
L H H L
H X X H
S-101
9 9
2 8 9 9
OUT P UT S OUT P UT S
Y 2 Y 1 Y 0
H H L
H L H
L H H
H H H
H H H