Denon S-101 Service Manual page 26

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3 7 63 1515 0
T431616A-8S(RL-S874:U5)
TE
L 13942296513
PIN DESCRIPTION
PIN
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A10/AP Address
BA Bank Select Address
RAS
Row Address Strobe
Column Address Strobe
CAS
Write Enable
WE
L(U)DQM Data Input/Output Mask
Data Input/Output
DQ0 ~ DQ15
V /V Power Supply/Ground
DD SS
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Data Output Power/Ground
V /V
DD Q SSQ
No Connection/Reserved
N.C/RFU
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V 1
DD
DQ0 2
DQ1 3
V 4
SSQ
DQ 2 5
DQ 3
6
V
DDQ
7
DQ 4 8
DQ 5 9
V
SSQ
10
DQ 6 11
12
DQ 7
V 13
DDQ
LDQM
14
WE
15
CAS
16
RAS
17
CS
18
BA
19
A10/AP
20
A0
21
A1
22
A2
23
A3
24
V
DD
25
PIN NAME
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Powe and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
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This pin is recommended to be left No Connection on the device.
for Future Use
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2 9
8
50
V
SS
49
DQ15
48
DQ14
47
V
SSQ
46
DQ13
45
DQ12
44
V
DDQ
43
DQ11
42
DQ10
41
V
SSQ
40
DQ 9
39
DQ 8
38
V
DDQ
37
N.C / RFU
36
UD QM
35
CL K
34
CK E
33
N.C
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
V
SS
Q Q
3 6 7 1 3 1 5
DESCRIPTION
after the clock and masks the output.
SHZ
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26
9 4 2 8
0 5 8 2 9 9 4 2 8
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S-101
9 9
9 9