Pci Slot Configuration - SOYO SY-7VBA 133 User Manual

BIOS Setup Utility

3-6.3 PCI Slot Configuration

PCI Slot
Configuration
CPU to PCI
Write Buffer
PCI Dynamic
Bursting
PCI Master 0
WS Write
PCI Delay
Transaction
PCI #2 Access
#1 Retry
AGP Master 1
WS Write
Setting Description
Disabled When this field is Enabled, writes
from the CPU to the PCI bus are
Enabled
buffered, to compensate for the
speed differences between the CPU
and the PCI bus. When Disabled,
the writes are not buffered and the
CPU must wait until the write is
complete before starting another
write cycle.
Disabled When Enabled, every write
transaction goes to the write buffer.
Enabled
Burstable transactions then burst on
the PCI bus and nonburstable
transactions don't.
Disabled
Enabled When Enabled, writes to the PCI
bus are executed with zero wait
states.
Disabled The chipset has an embedded 32-bit
posted write buffer to support delay
Enabled
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
Disabled When PCI#2 (AGP bus) access to
PCI#1 (PCI bus) has a error
Enabled
occurred.
Disabled
Enabled When Enabled, writes to the
AGP(Accelerated Graphics Port) are
executed with one wait states.
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SY-7VBA 133
Note
Default
Default
Default
Default
Default
Default