Memory Hole - MSI ATX BX2 User Manual

DRAM Refresh Rate
This option is for setting the frequency of refreshing the DRAM.
Available settings are 15.6, 31.2, 62.4, 124.8, and 249.6 us.

Memory Hole

This option allows the end user to specify the location of a memory
hole. The cycle matching the selected memory hole will be passed to the
ISA bus. If Enabled, the selected hole is not remapped.
VGA Frame Buffer USWC
The Pentium
Write-Combining (USWC) memory type. The processor provides a write-
combining with buffering strategy for write operation. This is useful for
frame buffering. Writing to USWC memory can be buffered and combined in
the processors write-combining buffer (WCB). The WCBs are viewed as a
special purpose outgoing write buffers, rather than a cache. The WCBs are
written into memory to allocate a different address, or after executing a
serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
B000 and BFFF segment as USWC memory type.
PCI Frame Buffer USWC
The Pentium
Write-Combining (USWC) memory type. The processor provides a write-
combining with buffering strategy for write operation. This is useful for
frame buffering. Writing to USWC memory can be buffered and combined in
the processors write-combining buffer (WCB). The WCBs are viewed as a
special purpose outgoing write buffers, rather than a cache. The WCBs are
written into memory to allocate a different address, or after executing a
serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
from main memory to 4GB segment as USWC memory type.
®
II processor supports the Uncacheable Speculatable
®
II processor supports the Uncacheable Speculatable
4-11
®