Dram Integrity Mode - MSI ATX BX2 User Manual

Description of the item on screen follows:
Configure SDRAM Timing by SPD
Enabling this option will set the SDRAM timing value to the value
provided by the DIMM SPD, otherwise, value will be set to the values you
set.
Note: It is recommended that under 100MHz, you use DIMM with SPD.
SDRAM RAS# to CAS# Delay
This operation decide the delay in assertion of CAS#(SCAS#) from
assertion of RAS#(SRAS#) in 66MHz. Under 66MHz CPU bus, set this
option to either 2 or 3 but for 100MHz CPU, it is recommended that this be
set to 3.
SDRAM RAS Precharge
This option defines the RAS# precharge requirements for the
SDRAM memory type in 66MHz clocks. Under 66MHz CPU bus, set this
option to either 2 or 3 but for 100MHz CPU, it is recommended that this be
set to 3.
SDRAM CAS# Latency
This option determines the CAS latency time parameter of SDRAM.
The settings are 2 clks or 3 clks. Under 66MHz CPU bus, set this option to
either 2 or 3 but for 100MHz CPU, it is recommended that this be set to 3.
SDRAM Leadoff Cmd Timing
This control the SDRAM command for CPU cycles. When this is
set to Auto, timing value is set on the value provided by SPD; 4 to 100MHz;
and 3 to 66MHz.

DRAM Integrity Mode

During ECC, this will enable the DRAM ECC mechanism that allows
single bit error detection and recovery. During EC mode, it will detect multi-
bit errors but cannot perform correction.
®
4-10