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Clock for URSA7
8pF
C1903
8pF
C1904
SPI Flash
+3.3V
R1909
10K
R1903
33
SPI_CZ
R1904
33
SPI_DO
1K
R1905
UART2_TX
OPT
R1910
10K
FLASH_WP
R1939
0
FLASH_WP_U
OPT
I2C EEPROM
+3.3V
IC2007
R1EX24256BSAS0A
A0
VCC
1
8
A1
WP
2
7
A2
SCL
3
6
VSS
SDA
4
5
I2CM_SCL_EEPROM
I2CM_SDA_EEPROM
Chip Config
Debug/ISP ADDR
Slabe (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V
10K
OPT
R1908
10K
R1902
OPT
10K
R1907
10K
R1901
OPT
10K
10K
R1906
R1900
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
XIN_URSA
XO_URSA
L1900
MLB-201209-0120P-N2
IC1901
C1901
MX25L3206EM2I-12G
0.1uF
25V
CS#
VCC
1
8
SO/SIO1
HOLD#
2
7
WP#
SCLK
R1919
33
SPI_CK
3
6
GND
SI/SIO0
R1920
33
SPI_DI
4
5
4MByte
C1900
0.1uF
25V
I2CM_SCL_EEPROM
I2CM_SDA_EEPROM
R1913
33
I2CM_SCL_URSA
R1911
33 OPT
I2CM_SCL1_URSA
R1916
33
I2CM_SCL_M_Port
R1915
33
I2CM_SDA_URSA
R1912
33 OPT
I2CM_SDA1_URSA
R1914
33
I2CM_SDA_M_Port
DIM0
DIM1
DIM2
URSA Reset
+3.3V
SW1901
JTP-1127WEM
1
2
OPT
C1902
22uF
3
4
10V
URSA7_Reset
0
R1924
Debugging for URSA
I2C_S Port
P1905
12507WS-04L
WAFER-STRAIGHT
SW1902
1
JS2235S
2
1
6
SCL_M1_A
SDA_M1_A
R1958
R1959
R1922
33
3
0
0
SCL2_+3.3V_DB
URSA_MP
URSA_MP
URSA_DEBUG
2
5
I2CS_SCL
I2CS_SDA
R1960
URSA_DEBUG
R1961
R1921
33
0
0
4
SDA2_+3.3V_DB
OPT
OPT
3
4
URSA_DEBUG
SDA2_+3.3V_DB
SCL2_+3.3V_DB
5
I2C_M Port
P1908
12507WS-04L
WAFER-STRAIGHT
1
2
3
I2CM_SCL_M_Port
4
I2CM_SDA_M_Port
5
IC2500
LGE7410
AA28
URSA7_Reset
RESET
VSYNC_LIKE2
AM3
XIN_URSA
XTALO
VSYNC_LIKE3
AL3
XO_URSA
XTALI
SPI1_CK/PWM2/GPIO58
AJ22
R1963
33
I2CS_SDA
I2CS_SDA
SPI1_DI/PWM3/GPIO59
R1964
AH23
33
I2CS_SCL
I2CS_SCL
SPI2_CK/PWM0/GPIO56
SPI2_DI/PWM1/GPIO57
AG24
I2CM_SDA_URSA
I2CM_SDA
SPI3_CK/DIM10/GPIO54
AG25
I2CM_SCL_URSA
I2CM_SCL/VSYNC_LIKE1
SPI3_DI/DIM11/GPIO55
SPI4_CK/DIM8/GPIO52
33
E8
R1929
UART2_TX
UART2_TX
GPIO[0]/UART2_TX
SPI4_DI/DIM9/GPIO53
33
D8
R1927
UART2_RX
UART2_RX
GPIO[1]/UART2_RX
VSYNC_LIKE/PWM5/GPIO40
D9
R1928
33
UART1_TX
UART1_TX
GPIO[2]/UART1_TX
33
E9
R1926
UART1_RX
UART1_RX
GPIO[3]/UART1_RX
DIM0/GPIO[32]
DIM1/GPIO[33]
AE31
SPI_CZ
SPI_CZ
DIM2/GPIO[34]
AD30
SPI_CK
SPI_CK
DIM3/GPIO[35]
AD32
SPI_DI
SPI_DI
DIM4/GPIO[36]
AE32
SPI_DO
SPI_DO
DIM5/GPIO[37]
DIM6/GPIO[38]
R1930
0
AB29
URSA7_stable
INT_R21/GPIO[41]
DIM7/GPIO[39]
33
AA29
OPT
R1933
INT_R20/GPIO[42]
AH25
OPT
R1931
33
GPIO[10]/PWM_DIM_IN[0]
AG26
OPT
R1932
33
GPIO[11]/PWM_DIM_IN[1]
NC_21
NC_22
F8
OPT
R1934
33
IRE
NC_23
NC_24
NC_25
AA26
TESTPIN
NC_26
AA27
GND_EFUSE
NC_27
NC_28
VX1T_HTPDN
VX1T_LOCKN
I2CM_SDA1
I2CM_SCL1
TGPIO12
3D_FLAG
TGPIO14
TGPIO15
IC2500
LGE7410
AH28
GPIO[8]/HDMIRX_CEC
AH29
GPIO[9]/HDMIRX_HPD
AJ27
GPIO[6]/DDCDA_CK
AJ28
GPIO[7]/DDCDA_DA
AH32
HDMI_RXCP
AH31
HDMI_RXCN
AG32
HDMI_RX0P
AG30
HDMI_RX0N
AF30
HDMI_RX1P
AG31
HDMI_RX1N
AE30
HDMI_RX2P
AF31
HDMI_RX2N
AH26
GPIO[4]/HDMITX_CEC
AH27
GPIO[5]/HDMITX_HPD
AJ25
HDMITX_SCL
AJ26
HDMITX_SDA
AL31
HDMITX_CLKP
AM31
HDMITX_CLKN
AK31
HDMI_TX0P
AL32
HDMI_TX0N
AJ30
HDMI_TX1P
AK32
HDMI_TX1N
AH30
HDMI_TX2P
AJ31
HDMI_TX2N
EAX65309301
U_UART,GPIO
AH24
AJ24
AE28
AE29
AF28
AE27
AG29
AF27
R1944
33
AG27
L_DIM_EN
AG28
AD27
AH20
DIM0
AG20
DIM1
AJ21
DIM2
AH21
R1945
33 OPT
AG21
R1950
33 OPT
AG22
R1940
33 OPT
AH22
R1935
33 OPT
AG23
R1951
33 OPT
E7
F7
D6
D5
E6
E5
F6
F5
AF4
AE4
AF5
R1936
0
I2CM_SDA1_URSA
AG4
R1946
0
I2CM_SCL1_URSA
AG5
R1941
33 OPT
AH4
R1937
0
AH5
R1942
33 OPT
AJ5
FLASH_WP_U
2013.03.18
20
22
LGE Internal Use Only
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