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XTAL(24.75MHz)
R12007
1M
X12000
24.75MHz
X-TAL_1
GND_2
XTAL_IN
1
4
GND_1
X-TAL_2
2
3
C12000
C12003
27pF
27pF
50V
50V
JTAG for HEVC
+3.3V_NORMAL
P12000
12507WS-08L
C12001
0.1uF
1
16V
2
R12000
33
D13_TDI_1
3
R12001
33
D13_TMS_1
4
R12002
33
D13_TCK_1
R12004
33
5
D13_TDO_1
R12003
33
6
D13_TRST_N_1
7
8
9
UART For HEVC
+3.3V_NORMAL
P12001
12507WS-04L
1
R12005
33
2
D13_UART_RX_1
3
R12006
33
4
D13_UART_TX_1
5
C12002
0.1uF
16V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HEVC option sheet
XTAL_OUT
+3.3V_NORMAL
+3.3V_NORMAL
R12009
R12020
10K
10K
OPT
OPT
D13_SMODE[0]
D13_SMODE[1]
R12013
R12021
10K
10K
SMODE[1:0]
- 00 : Normal Mode
- Other : Test Mode
+3.3V_NORMAL
R12010
10K
D13_SPI_CS/GPIO[0]
R12011
10K
OPT
GPIO[0]
- 1 : Serial Flash Boot
- 0 : Live Boot
Serial Flash Boot Test
+3.3V_NORMAL
P12002
12507WS-10L
R12043
1K
1
R12038
0
2
D13_SPI_CS/GPIO[0]
R12039
0
3
D13_SPI_DO_M
R12040
0
4
D13_SPI_SCLK_M
R12041
0
5
D13_SPI_DI_M
R12042
0
6
SPI_DL_MODE
OPT
7
R12044
0
OPT
8
R12045
0
D13_FLASH_WP
R12046
0
9
I2C_SDA2
R12047
0
10
I2C_SCL2
11
+3.3V_NORMAL
R12050
33
R2
XTAL_IN
XTALI
R12016
R1
3.3K
XTAL_OUT
XTALO
R12051
R12014
33
A18
33
D13_RESET
PORES_N
SPI_DL_MODE
E1
D13_TRST_N_0
TRST_N0
C3
C12004
D13_TMS_0
TMS0
0.01uF
D1
D13_TCK_0
TCK0
B1
D13_TDI_0
TDI0
D3
D13_TDO_0
TDO0
E2
D13_TRST_N_1
TRST_N1
B3
D13_TMS_1
TMS1
D2
D13_TCK_1
TCK1
B2
D13_TDI_1
TDI1
D13_TRST_N_0
C2
D13_TDO_1
TDO1
D13_TMS_0
D13_TCK_0
B10
D13_UART_RX_0
UART_RXD0
D13_TDI_0
A10
D13_UART_TX_0
UART_TXD0
D13_TDO_0
B9
D13_UART_RX_1
UART_RXD1
D13_UART_RX_0
A9
D13_UART_TX_1
UART_TXD1
D13_UART_TX_0
C20
SOC_SPI0_SCLK
SPI_SCLK_S
D20
SOC_SPI0_CS0
SPI_CS_S
D19
SOC_SPI0_MOSI
SPI_DO_S
C19
R12024
33
SOC_SPI0_MISO
SPI_DI_S
A14
R12025
33
D13_SPI_SCLK_M
SPI_SCLK_M
B14
R12026
33
SPI_CS_M
B13
R12027
33
D13_SPI_DO_M
SPI_DO_M
A13
D13_SPI_DI_M
SPI_DI_M
OPT
A11
R12028
33
SCL_S
OPT
B11
R12029
33
SDA_S
A12
R12030
33
I2C_SCL2
SCL_M
OPT
B12
R12031
33
I2C_SDA2
SDA_M
OPT
G20
R12008
33
D13_STPO_CLK
STPI_CLK
H19
R12012
33
D13_STPO_SOP
STPI_SOP
G19
R12022
33
D13_STPO_VAL
STPI_VAL
H20
R12023
33
D13_STPO_ERR
STPI_ERR
J19
R12033
33
D13_STPO_DATA
STPI_DATA[0]
J20
STPI_DATA[1]
C12261
K19
STPI_DATA[2]
10pF
K20
STPI_DATA[3]
L19
STPI_DATA[4]
L20
STPI_DATA[5]
M19
STPI_DATA[6]
M20
STPI_DATA[7]
SPI FLASH(4MByte)
D13_SPI_CS/GPIO[0]
D13_SPI_DI_M
D13_FLASH_WP
R12049
10
IC12000
D13_INT
LG1132-D13
+3.3V_NORMAL
IC_D13
B7
GPIO[7]
A7
GPIO[6]
B6
GPIO[5]
A6
GPIO[4]
B5
GPIO[3]
A5
GPIO[2]
B4
GPIO[1]
A4
GPIO[0]
G1
D13_HDMI_DDC_CK
HDMI_DDC_CK
G2
HDMI_DDC_DA
D13_HDMI_DDC_DA
J2
HDMI_HPD
D13_HDMI_HPD
J1
HDMI_REXT
H2
HDMI_CEC
H1
HDMI_DDCCEC
M1
HDMI_TX0N
D13_HDMI_TX0N
M2
HDMI_TX0P
D13_HDMI_TX0P
L1
HDMI_TX1N
D13_HDMI_TX1N
L2
D13_HDMI_TX1P
HDMI_TX1P
K1
D13_HDMI_TX2N
HDMI_TX2N
K2
HDMI_TX2P
D13_HDMI_TX2P
N1
HDMI_TXCN
D13_HDMI_TXCN
N2
HDMI_TXCP
D13_HDMI_TXCP
F2
D13_SMODE[0]
SMODE[0]
E3
D13_SMODE[1]
SMODE[1]
A16
TMODE[0]
B16
TMODE[1]
A17
TMODE[2]
B17
TMODE[3]
* Default Internal Pull-Up
+3.3V_NORMAL
IC12001
MX25L3206EM2I-12G
R12017
10K
CS#
VCC
1
8
R12019
SO/SIO1
HOLD#
R12032
2
7
33
3.3K
R12015
WP#
SCLK
0
3
6
1/16W
R12018
10K
5%
GND
SI/SIO0
OPT
4
5
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
H/W Option : default low
SPI Clock Frq. &
DDR density
(High:512MB, LOW:256MB)
D13_FLASH_WP
D13_SPI_CS/GPIO[0]
R12037
1.6K 1%
Closed to D13
C12005
0.1uF
D13_SPI_SCLK_M
D13_SPI_DO_M
LGE Internal Use Only
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