Revision History - Intel 41210 User Manual

Serial to parallel pci bridge evaluation board
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Revision History

Date
October 2004
December 2003
iv
Revision
-Updated naming terminology in Sections 2.0 and 3.0.
-Corrected PCI Bus name Header Connectors J5 and J6 in
002
Section 4.0.
-Corrected Switch S3 and S4 PCI-X 66 MHZ Pos 3 settings in
Table 1.
001
This is the first release of this document.
Description
User's Guide

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