Basic Operation; Stair Generation - Sony UP-895 Service Manual

INTV
0
STB
64CLK
CLK
5.75 MHz
1st stair 2nd stair
DATA1-16
DATA
DATA
64 data is transferred to head 1 block.
In all, data is transferred in parallel to 20 blocks.
(64 data x 20 = 12800 data)
DR

4-5-2. Basic Operation

Various signals are input from the memory and head control circuit (IC501) to the head. This section
describes the operation in only one block. (The operation in other blocks is also the same as described
above.)
(1) Print data (64 data) is input to the shift register section in synchronization with a clock.
(2) When a STB pulse is input, the data input in step (1) is moved from the shift register section to the
latch section.
(3) When a DR pulse is input, the output-stage transistors are turned on and off by the "H" and "L" data
in the latch section. The resistors then heat up and the thermosensitive paper changes color. The
amount of heat generated is controlled by changing the length of the DR pulse, so the color darkness
of the printing on thermosensitive paper can be changed.
n
The BEO terminal goes from "L" to "H" when starting the print and goes from "H" to "L" when print is
ended.

4-5-3. Stair Generation

As explained in the last section on basic operation, the darkness of the printing can be controlled using a
DR pulse, it is also possible to change the darkness by changing the "H" and "L" data input to the latch
section. The method is described below.
(1) One-line image data recorded in image memory SDRAM (IC503) is fetched to the line memory in
IC501 every print operation one line (nPRINT_PULSE) by controlling a memory and head control
circuit (IC501).
(2) The data fetched to the line memory is input to the stair generator circuit in IC501. The stair data
generator circuit outputs the 8-bit data fetched to the line memory as stair data 1 through 64. If 8-bit
data is 128, "H" data is output to the head in the 1st through 32nd stairs of data 1 through 16. "L"
data is output in the 33 rd and later stairs.
(3) The data output from the data generator circuit to the head is transferred to the shift register section of
the head in synchronization with the clock output from IC501.
UP-895/(E)
1 2 3
T T T
0 1 2
3rd stair 4th stair 5th stair
DATA DATA DATA
1
Stair Generation
4 61
T
T T
3 4 61
62nd stair 63th stair 64th stair
DATA DATA
62 63
T T
62 63
DATA
4-15