HP Kayak XU800 Technical Reference Manual page 36

Feature
Processor/Host Bus:
•
Supports up to two Pentium III processors at: 100 MHz/133
MHz Host Bus frequency.
Supports full Symmetric Multiprocessor (SMP) Protocol for
up to two processors.
Provides an 8-deep In-Order Queue supporting up to eight
outstanding transaction requests on the host bus.
Desktop optimized GTL+ bus driver technology (gated GTL+
receivers for reduced power).
Support for 36-bit host bus address.
IERR and BERR signals generate SCi/SERR.
Parity protection on address and resource signals:
Parity errors generate SERR.
Memory Controller.
•
Direct Rambus:
Dual Direct Rambus Channels operating in lock-step (both
channels must be populated with a memory module).
Supporting 300 MHz or 400 MHz.
RDRAM 64 Mb, 128 Mb, 256 Mb devices.
Minimum upgrade increment of 16 MB using 64 Mb DRAM
technology.
Up to 64 Direct Rambus devices (without using MRH-R).
Dual channel maximum memory array size is:
— 512 MB using 64 Mb DRAM technology.
— 1 GB using 128 Mb DRAM technology.
— 2 GB using 256 Mb DRAM technology.
Up to 8 simultaneous open pages:
— 1 KByte page size support for 64 Mbit, 128 Mbit and 256
Mbit RDRAM devices.
— KByte page size support for 256 Mbit RDRAM devices.
Hub Link 8-bit Interface to ICH:
•
High-speed interconnect between the MCH and ICH
(266 MB/sec).
2 System Board
Memory Controller Hub (8240)
The following table shows the features that are available in the MCH Host
Bridge/Controller.
36
Feature
Accelerated Graphics Port (AGP) Interface:
•
Single Universal AGP PRO connector.
AGP Rev 2.0 compliant, including AGP 4x data transfers and
2x/4x Fast Write protocol.
AGP Universal Connector support via dual mode buffers to al-
low AGP 2.0 3.3 V or 1.5 V signalling.
AGP PIPE# or SBA initiated accesses to DRAM is not
snooped
AGP FRAME initiated accesses to DRAM are snooped
(snooper identifies that data is coherent in cache memory).
Hierarchical PCI configuration mechanism.
Delayed transaction support for AGP-to-DRAM reads that
cannot be serviced immediately.
SDRAM:
Up to 8 GB of SDRAM using four external Memory Repeater
Hubs for SDRAM (MRH-S).
Currently, two MRH-S devices are supported.
Interleaved 100 MHz support using 4 MRH-S for a maximum
bandwidth.
Non-Interleaved 100 MHz support using 2 MRH-s for lower
cost and upgrade path.
Unbuffered DIMMs are supported.
Up to 4 rows or 2 DS DIMMs per MRH-S.
Up to 8 simultaneous open pages:
— 2 KByte page size support for 64 Mbit SDRAM devices.
— 4 KByte - 16 KByte page sizes supporting 64 MBit to
256 Mbit SDRAM devices.
Configurable optional ECC operation:
— ECC with single bit Error Correction and multiple bit Error
Detection.
— Single bit errors corrected and written back to memory
(scrubbing).
Hub Link 16-bit Interface to P64H:
•
High-speed interconnect between the MCH and P64H
(533 MB/sec).