Dv_Main Schematic Diagram - JVC GR-D30UB Specification

DV_MAIN SCHEMATIC DIAGRAM

MAIN ( DV_MAIN )
TO DSC
TL3007
TL3008
TL3009
5
TO CAM_DSP
TL3011
TO REG L3002
REG_3.1V
NQR0129-002X
REG_2.5V
REG_1.8V
C3003
1
GND
L3005
NQR0006-001X
C3007
4 10
L3004
NQR0006-001X
C3005
10 /6.3
T
D3004 L3001
RB751V-40-X NQR0129-002X
C3001
10 /6.3 T
3
L3012
NQR0129-002X
R3025
1K
Q3001
C3008
2SC4617 10 /6.3
C3009
1
C3006 R3026
1 OPEN
2
TO PREMDA
AGC_OUT
VRB_AGC
VREF_1.1
REC_DATA
REC_CLK
REC_CTL
REF_CLK
ATFI
VRB_ATF
L3015
NQR0006-001X
1
NOTE: The parts with marked ( ) is not used.
A
TDO
TMS
TCMK
TRST
TDBI
N.C
N.C
C3047 0.1
MON0
MON1
VDDE
VDDI
MON2
MON3
MON4
MON5
VSS
MON6
MON7
MON8
MON9
MON10
C3042
0.01 MON11
MON12
C3043 VDDE
VDDI
0.01
MON13
MON14
MON15
MON16
MON17
MON18
MON19
VSS
MON20
MON21
MON22
MON23
VDDE
MON24
MON25
MON26
MON27
VDDE
C3044 0.1
N.C
VDDP
VSSP
VDDA
VSS
N.C
N.C
VDDE
VSS
VSS
VDDE
VDDI
VSS
VDDE
VDDE
VDDI
VSS
VSS
MTEST
C3045 0.1
PHYAVD2
BUSRST
RA3004 10k
PHYAVS2
PMODE
PWR3
PWR1
PWR2
T
VDDI
PHYAVS1
PHYAVD3
C3046 0.01
PHYAVD1
VSS
VDDE
VDDI
VSS
R3071 0
C3011
0.1
R3073
OPEN
2SC4617
Q3002
R3074
10K
C3056
OPEN
R3072
OPEN
B C
CPUBUSTYPE
CPUDSLOGIC
CPUWAITLOGIC
XCPUDSTB1
XCPUDSTB0
IC3001
JCY0152
L3007
µ
2.2
CH
R3009
10k
R3010
10k TL3001
R3075 OPEN
L3014
µ
10
R3068
IC3002
180
BU2501FV-X
C3068
OPEN
C3067
1000P
T
C3070 C3069
C3059
OPEN 0.1 22 /4
D E
2-11 2-12
R3021
0
R3022 OPEN
CPUWAIT
XINT
XCPUCS
XCPURW
CPUALE
INV
INH
OUTV
OUTH
BRSI3
BRSI2
BRSI1
BRSI0
YSI3
YSI2
YSI1
YSI0
BRSO3
BRSO2
BRSO1
BRSO0
YSO3
YSO2
YSO1
YSO0
AODAT0
AODAT1
VSS
AOBCK
AOLRCK
DODAT
C3038 0.1
VDDI
DOBCK
DOLRCK
C3040 OPEN
AIDAT0
AIDAT1
AIMCK
AIBCK
AILRCK
DIDAT
R3034
DIMCK R3082 *
2.2k
DIBCK
R3081 *
DILRCK
OSC11O
R3083 *
OSC11I
C3037
OSC24O
8P
X3002
OSC24I
C3036
VCXO12O
8P
VCXO12I
[NAX0480-001X]
VCXO11O
L3008
µ
VCXO11I 12
C3031 0.1
VDDP
C3030 0.1
CH
VCIAUD C3032 C3033
0.001 12P
VSSP
VDDE
PWMAUDIO
R3027
VSS
10k
VDDE
N.C
C3049
2200P
LPFIN
R3029
15K
LPFOUT
R3036 R3037
C3048
VDDE
10K 680
0.047
PHYAVS3
PHYVSR
C3029
PHYVSA 0.01
PHYVDR
PHYVDA
C3050
0.01
CH
F
TO CPU
XINT
DV_CS
TO CAM_DSP
INV
INH
R3005 10
OUTV
R3006 10
OUTH
DCO3
DCO2
DCO1
DCO0
DYO3
DYO2
DYO1
DYO0
DCI3
RA3001
DCI2
47
DCI1
DCI0
DYI3
RA3002
DYI2
47
DYI1
DYI0
CLK27A
TO AV_STRM
PIX_ACLK
TO AUDIO
RA3003 AODAT
AIDAT
AIMCK
AIBCK
AILRCK
10
TO CPU
ADDT15
ADDT15
ADDT14
ADDT14
ADDT13
ADDT13
ADDT12
ADDT12
ADDT11
ADDT11
ADDT10
ADDT10
ADDT09
ADDT09
ADDT08
ADDT08
ADDT07
ADDT07
ADDT06
ADDT06
ADDT05
ADDT05
ADDT04
ADDT04
ADDT03
ADDT03
ADDT02
ADDT02
ADDT01
ADDT01
ADDT00
ADDT00
DV_WAIT
DRWSEL
CDDSTB
CDWE
CDALE
DV_RST
CLK27SEL
SRV_TRK
TSR
FRP
SPA
HID1
TL3006
TO JIG CONN
FS_PLL
MAIN_VCO
PB_CLK
DISCRI
RA3005 0Ω
TO DV_IN/OUT
NRZ0040-0R0X
J501
DUMP_CTL
NOSIG_LV
TO PREMDA
ATF_GAIN
RECCADJ
VIFD_OUT
VIFD_CLK TO CPU
DAC_CS
H_OFFSET
TO OP_DRIVER
H_GAIN
y10333001a_rev0.1
G