LA1837 INTERNAL IC DIAGRAM
30
29
28
27
26
25
REG
AM
AM
ALC
AM
MIX
RF.AMP
OSC
BUFF
AGC
AM IF
DET
SD
COMP
AM
S-METER
FM
AM/FM
S-CURVE
S-METER
IF-BUFF
TUNING
DRIVE
FM
AM IF
DET
GND
1
2
3
4
5
6
ESS4008 INTERNAL IC DIAGRAM
SRAM
Interface
G P IO
TDM
Transport
Interface
S erial A udio
Interface
8-2
24
23
22
21
20
19
18
17
3 rd 5 th
DECODER
ANTI-BIRDIE
MUTE
P-DET
STEREO
SW
VCO
FF
FF
FF
PILOT
304kHz
38K
19k
19k
DET
2
STEREO
DRIVE
VCC
7
8
9
10
11
12
13
14
32-B i t
R ISC
Processor
16 K Cache
G ateway
+
D M A
C ontroller
Huffm an
DRAM
Decoder
Interface
SIM D
DSP
R O M
RAM
SYNCHRONOUS DRAM
1MX16Y3VTW
16
PIN ASSIGNMENT (Top View)
50 - Pin TSOP
V
1
DD
DQ0
2
DQ1
3
VssQ
4
DQ2
5
DQ3
6
V
Q
7
DD
DQ4
8
DQ5
9
VssQ
10
DQ6
11
DQ7
12
V
Q
13
DD
DQML
14
WE#
15
CAS#
16
RAS#
17
CS#
18
BA
19
A10
20
A0
21
A1
22
A2
23
A3
24
V
25
DD
15
FUNCTIONAL BLOCK DIAGRAM
1 Meg x 16 SDRAM
CKE
CLK
CS#
CONTROL
LOGIC
WE#
CAS#
RAS#
MODE REGISTER
12
REFRESH
ADDRESS
CONTROLLER
A0-A10, BA
12
REGISTER
REFRESH
COUNTER
11
8-2
50
Vss
49
DQ15
48
DQ14
47
VssQ
Note: The # symbol indicates signal is active LOW.
46
DQ13
45
DQ12
44
V
Q
DD
Configuration
43
DQ11
42
DQ10
Refresh Count
41
VssQ
Row Addressing
40
DQ9
Bank Addressing
39
DQ8
38
V
Q
DD
Column Addressing
37
NC
36
DQMH
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
h
26
Vss
BANK0
ROW-
MEMORY
11
ADDRESS
11
2,048
ARRAY
LATCH
(2,048 x 256 x 16)
256 (x16)
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
256
COLUMN
8
8
DECODER
256
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROW-
ADDRESS
256 (x16)
MUX
BANK1
ROW-
MEMORY
11
ADDRESS
11
2,048
ARRAY
LATCH
(2,048 x 256 x 16)
1 M eg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
DQML,
DQMH
DATA
OUTPUT
16
REGISTER
DQ0-
16
DQ15
16
DATA
INPUT
8
REGISTER