Contrast - Hitachi C15-LC880SNT Service Manual

INFORMATION OF ICS
IC SAA5264PS/M3/0104 SDIP52
Pin No. Pin Name
1 PWM
2 PWM0
3 PWM1
4 PWM2
5 PWM3
6 PWM4
7 PWM5
8 PWM6
9 ADC0
10 ADC1
11 ADC2
12 ADC3
13 V
SCC
14 SCL(NVRAM)
15 SDA(NVRAM)
16
17
18
19
20 Diodes (LEDs)
21
22 V
SSA
23 CVBS0
24 CVBS1
25 SYNC_FILTER
26 IREF
27 FRAME
28 TEST
29 COR
30 PWM7
31 V
DDA
32 B
33 G
34 R
35 VDS
36 HSYNC
Output for 14-bit high precision Pulse Width Modulator(PWM)
Output for 6-bit PWMs 0 to 6
Inputs for the software Analog-to-Digital-Converter(ADC) facility
Core ground
2
I C-bus Serial Clock input to Non-Volatile RAM
2
I C-bus Serial Data input/output (Non-Volatile RAM)
Input/output for general use
Input/output for general use
Input/output for general use
8mA current sinking capability for direct drive of Light Emitting
Input/output for general use
Analog ground
Composite Video Baseband Signal(CVBS) input; a positive-going
1 V (peak-to peak) input is required; connected via a 100 nF capacitor
Sync-pulse-filter input for CVBS; this pin should be connected to V
via a 100nF capacitor
Reference current input for analog circuits; for correct operation a
24kΩ resistor should be connected to V
Frame de-interlace output synchronized with the VSYNC pulse to
produce a non-interlaced display by adjustment of the vertical
deflection circuits
Not avallable; connect this pin to V
Contrast reduction:open-drain, active LOW output which allows selective
contrast reduction of the TV picture to enhance a mixed mode display
Output for 6-bit PWM7
Analog supply voltage (3.3V)
Blue colour information pixel rate output
Green colour information pixel rate output
Red colour information pixel rate output
Video/data switch push-pull output for pixel rate fast blanking
Horizontal sync pulse input: Schmitt triggered for a Transistor Transistor
Lever(TTL) version; the polarity of this pulse is programmable by
register bit TXT1.H POLARITY
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Description
SSA
SSA
SSA