Sony ZS-M7 Service Manual page 40

• BD BOARD IC121 digital signal processor, digital servo signal processor, EFM/ACIRC encoder/decoder, shock-
proof memory controller, ATRAC encoder/decoder, 2Mbit DRAM (CXD2652AR)
Pin No. Pin name
1 MNT0(FOK)
2 MNT1(SHCK)
3 MNT2(XBUSY)
4 MNT3(SLOC)
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11 SQSY
12 DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 TEST G
20 DVSS
21 DIN
22 DOUT
23 ADDT
24 DADT
25 LRCK
26 XBCK
27 FS256
28 DVDD
29–32 A03–A00
33 A10
34–38 A04–A08
39 A11
40 DVSS
41 XOE
42 XCAS
43 A09
44 XRAS
45 XWE
46 D1
47 D0
48, 49 D2,D3
50 MVCI
* In the I/O column, I(S) is Schmitt input, I(A) is analog input, O(3) is state output and O(A) is analog output.
I/O
FOK signal output to system control.
O
H is outputted when in focus.
O Track-jump detection signal output to system control.
O Monitor 2 output to system control.
O Monitor 3 output to system control.
I Write-data signal input from system control.
I(S) Serial clock signal input from system control.
I(S) Serial latch signal input from system control.
O(3) Read-data signal output to system control .
O(3) Internal status (SENSE) output to system control.
I(S) Reset signal input from system control. "L": Reset
Subcode Q-SYNC (SCOR) output to system control.
O
Majority of those which output "L" every 13.3 seconds output "H".
Subcode of digital-in U-bit CD format to system control.
O Majority of those which outputs "L" every 13.3 seconds during output of Q-SYNG
(SCOR) outputs "H".
I Laser power switch input from system control "H": Record, "L": Playback.
O Interrupt status output to system control.
I Record data output authorization input from system control.
I System clock input (512Fs = 22.5792MHz).
O System clock output (512FS = 22.5792MHz).
Pin for system clock frequency setting .
I
"L": 45.1584MHz "H": 22.5792MHz (Fixed at "H").
– Test terminal.
– Ground (digital system).
I Digital audio input (for optical input).
O Digital audio output (for optical output).
I Data input from A/D converter.
O Data output to D/A converter.
O LR clock output (44.1kHz) for A/D and D/A converters.
O Bit clock output (2.8224MHz) for A/D and D/A converters.
O 11.2896MHz clock output (unused).
– Power supply for digital (+3V).
O
O
DRAM address outputs.
O
O
– Ground for digital.
O DRAM output-enable output.
O DRAM CAS signal output.
O DRAM address output.
O DRAM RAS signal output.
O DRAM write-enable signal output.
I/O
I/O DRAM data I/O.
I/O
I(S) Clock input from external VCO (Fixed at "L").
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Description