Kenwood TK-7160 Service Manual page 13

■ Wide/Narrow Switching Circuit
The Wide port (pin 23) and Narrow port (pin 22) of the CPU
is used to switch between ceramic filters. When the Wide
port is high, the ceramic filter SW diodes (D332, D331) cause
CF301 to turn on to receive a Wide signal.
When the Narrow port is high, the ceramic filter SW di-
odes (D332, D331) cause CF302 to turn on to receive a Nar-
row signal.
IF_IN
CF301
(Wide)
CF302
(Narrow)
D332
Narrow
IC101 22pin
Fig. 3 Wide/Narrow switching circuit
■ AF Signal System
The detection signal from IF IC (IC321) goes to D/A con-
verter (IC201) to adjust the gain and is output to AQUA IC
(IC241) for characterizing the signal. The AF signal output
from IC241 and the DTMF/MSK signal, BEEP signal are
summed and the resulting signal goes to the D/A converter
(IC201). The AFO output level is adjusted by the D/A con-
verter. The signal output from the D/A converter is input to
the audio power amplifier (IC281). The AF signal from IC281
switches between the internal speaker and speaker jack (J1)
output.
IC321 IC201 IC241
W/NO
D/A
AQUA
IF IC
CONV.
Fig. 4 AF signal system
IC401 : PLL IC
PLL
DATA
REF
OSC
16.8MHz
CIRCUIT DESCRIPTION
IC321
IF System
MIX_O
R333
Wide
IC101
23pin
R332
D331
IC201 IC281 SP
D/A
AF PA
IC CONV.
5kHz/6.25kHz
1/N
Phase Charge
comparator pump
1/M
5kHz/6.25kHz
Fig. 6 PLL circuit
■ Squelch Circuit
The detection output from the FM IF IC (IC321) passes
through a noise amplifier (Q301) to detect noise. A voltage is
applied to the CPU (IC101). The CPU controls squelch ac-
cording to the voltage (SQIN) level. The signal from the RSSI
pin of IC321 is monitored. The electric field strength of the
receive signal can be known before the SQIN voltage is input
to the CPU, and the scan stop speed is improved.
Q301
IC321 NOISE AMP
AFO
IF
SYSTEM
RSSI
Fig. 5 Squelch circuit
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
■ PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC401 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output signal
is buffer amplified by Q446, then divided in IC401 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC401. The output signal from the
phase comparator is filtered through a low-pass filter and
passed to the VCO to control the oscillator frequency. (See
Fig. 6)
■ VCO
The operating frequency is generated by Q444 in transmit
mode and Q441 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D443 and
D444 in transmit mode and D441 and D442 in receive mode).
The TX/RX pin is set low in receive mode causing Q443 and
Q442 to turn Q444 off, and turn Q441 on. The TX/RX pin is
set high in transmit mode. The outputs from Q441 and Q444
are amplified by Q446 and sent to the RF amplifiers.
Q444
TX VCO
LPF
D443,444
Q441
RX VCO
D441,442
TK-7160
D301 IC101
SQIN
DET
CPU
RSSI
Q431
AMP
Q446
BUFF
AMP
Q442,443
T/R SW
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