Harman Kardon AVR247 Service Manual page 145

AVR247
PIN CONFIGURATION
PIN DESCRIPTION
PIN
CLK Clock
CKE Clock Enable
CS Chip Select
BA Bank Address
A0 ~ A10 Address
Row Address Strobe,
RAS, CAS, WE Column Address Strobe, Write
Enable
LDQM, UDQM Data Input/Output Mask
DQ0 ~ DQ15 Data Input/Output
V /V Power Supply/Ground
DD SS
V /V Data Output Power/Ground
DDQ SSQ
NC No Connection
Rev. 0.1 / Nov. 2003
V V 1 1
DD DD
DQ0 DQ0 2 2
DQ1 DQ1
3 3
V V
SSQ SSQ 4 4
DQ2 DQ2
5 5
DQ3 DQ3
6 6
V V
DDQ DDQ 7 7
DQ4 DQ4 8 8
DQ5 DQ5
9 9
V V
10 10
SSQ SSQ
11 11
DQ6 DQ6
12 12
DQ7 DQ7
13 13
50pin TSOP II 50pin TSOP II
VDDQ VDDQ
400mil x 825mil 400mil x 825mil
14 14
LDQM LDQM
0.8mm pin pitch 0.8mm pin pitch
15 15
/WE /WE
16 16
/CAS /CAS
17 17
/RAS /RAS
18 18
/CS /CS
19 19
A11 A11
20 20
A10 A10
21 21
A0 A0
22 22
A1 A1
23 23
A2 A2
24 24
A3 A3
25 25
V V
DD DD
PIN NAME
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.
Command input enable or mask except CLK, CKE and DQM
Select either one of banks during both RAS and CAS activity.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation.
Refer function truth table for details
DQM control output buffer in read mode and mask input data in write mode
Multiplexed data input / output pin
Power supply for internal circuit and input buffer
Power supply for DQ
No connection
V V
50 50
DQ15 DQ15
49 49
DQ14 DQ14
48 48
VSSQ VSSQ
47 47
DQ13 DQ13
46 46
DQ12 DQ12
45 45
VDDQ VDDQ
44 44
DQ11 DQ11
43 43
DQ10 DQ10
42 42
VSSQ VSSQ
41 41
DQ9 DQ9
40 40
DQ8 DQ8
39 39
VDDQ VDDQ
38 38
NC NC
37 37
UDQM UDQM
36 36
CLK CLK
35 35
CKE CKE
34 34
NC NC
33 33
A9 A9
32 32
A8 A8
31 31
A7 A7
30 30
A6 A6
29 29
A5 A5
28 28
A4 A4
27 27
VSS VSS
26 26
DESCRIPTION
145
harman/kardon
HY57V161610ETP-I
SS SS
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