SOYO SY-P4VDA User Manual page 43

BIOS Setup Utility
DRAM Clock/Drive Control (Continue)
DRAM Timing
SDRAM CAS
Latency
Bank Interleave
Precharge to
Active(Trp)
Active to
Precharge(Tras)
Active to
CMD(Trcd)
DRAM Burst Len
Setting
By SPD
Manual
2.5
2
Disabled
2 Bank
4 Bank
2T
3T
6T
5T
3T
2T
4
8
40
Description
If enable the DRAM will auto
detect the DRAM timing.
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency
depends on the DRAM
timing. Do not reset this field
from the default value
specified by the system
designer.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
Increase DRAM performance.
SY-P4VDA
Note
Default
Default
Default
Default
Default
Default
Default