SOYO SY-K7ADA XP User Manual page 64

BIOS Setup Utility
CHIPSET FEATURES SETUP (Continued)
CHIPSET Setting
FEATURES
Auto (By SPD)
DRAM CAS
Select
2.5 (DDR) / 3 (SDR)
2 (DDR) / 2 (SDR)
DARM Auto (By SPD)
Performance
Failsafe
Slow
Normal
Fast
Ultra
Ultra2
7.16 MHz
AT Bus Clock
CLK2/2
CLK2/3
CLK2/4
CLK2/5
CLK2/6
System BIOS Disabled
Cacheable
Enabled
Description
When synchronous
DRAM is installed, the
number of clock cycles of
CAS latency depends on
the DRAM timing. Do not
reset this field from the
default value specified by
the system designer.
This item allow you to
control the DRAM timing.
This item allow you to
control the ISA Bus clock.
The ROM area
F0000H-FFFFFH is
cacheable.
60
SY-K7ADA XP
Note
Default
Default
Default
Default