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Automatically Set at
Power On Conditions
Automatically Set by
Parser
Set by *OPC
Related Commands
are *OPC? and *WAI
0
1
2
3
4
5
6
7
Scan Complete
8
9
10
11
12
13
14
15
C
Figure 4-1. E1465A/E1466A/E1467A Status System Register Diagram
Chapter 4
Output Queue
Standard Event Status Register
*ESR?
Power On
0
<1>
User Request
1
<2>
Command Error
2
<4>
Execution Error
3
<8>
Device Dependent Error
4
<16>
Query Error
5
<32>
Request Control
6
<64>
Operation Complete
7
<128>
EV
EN
OPERation Status Register
STATus:OPERation:CONDition?
STATus:OPERation:EVENt?
STATus:OPERation:ENABle
STATus:OPERation:ENABle?
STATus:PRESet
<1>
<2>
<4>
<8>
<16>
<32>
<64>
"OR"
<128>
+
<256>
<512>
<1024>
<2048>
<4096>
<8192>
<16384>
<32768>
EV
EN
*ESE <unmask>
Status Byte Register
*ESE?
*STB?
SPOLL
"OR"
+
0
1
2
Summary
3
Bit
MAV
4
ESB
5
RQS
6
OPR
7
Status
Byte
Summary Bit
Summary
Bit
Operation Complete
*ESE 61 unmasks standard event register bits 0,
2, 3, 4 and 5 (*ESE 128 only unmasks bit 7).
*SRE 128 unmasks the OPR bit (operation) in
the status byte register. This is effective
only if the STAT:OPER:ENAB 256 command
is executed.
STAT:QUES:ENAB 256 unmasks the "Scan Complete"
bit.
Matrix Modules Command Reference 69
NOTE:
QUE = Questionable Data
MAV = Message Available
ESB = Standard Event
RQS = Request Service
OPR = Operation Status
C = Condition Register
EV = Event Register
EN = Enable Register
SRQ = Interface Bus
Service Request
*SRE <unmask>
*SRE?
<1>
<2>
<4>
"OR"
<8>
+
<16>
<32>
System
Controller
<128>
Interface Bus
EN
SRQ Line
SRQ
SRQ
Instrument
SRQ
Instrument
unmask examples:
unmask
Register
decimal
bit
weight
"OR"
+
7
<128>
Other
Other
ESB
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