Agilent Technologies E1465A User Manual page 48

Card
Add
Add
Bus
Detector
Sysreset Card
& Control Reset &
Bus Logic
DTACK
VME
Timing
PAL
IRQ*
Data
Data
Bus
Bus
Buffer
48 Using the Matrix Modules
•
The FIFO Interface PAL reads the Data Bus and Address Bus
FIFO until the EMPTY* flag signals the FIFO Interface PAL the
FIFO memory is empty.
•
When the FIFO is empty, the FIFO Interface PAL signals the VME
Timing PAL which asserts IRQ*. This interrupts the command
module CPU after the last relay has been activated.
•
Because the matrix module asserts IRQ* after the last relay is
activated, the CPU is not continually interrupted. Thus, system
throughput is enhanced.
Address
Bus
FIFO
Empty *
Card Reset*
Data
Bus
FIFO
Device
ID
Register
Status &
Control
Register
Figure 3-3. Matrix Modules Block Diagram
Add
Decoder
Driver
& One Shot
FIFO-Write
FIFO
Interface FIFO-Read
PAL
Data
Bus
Driver
Power
Power
Latching
Relay
Ground
Chapter 3