Trigger Circuit; Digital Circuit - Fluke 43B Service Manual

An offset compensation voltage and a trace position control voltage are provided by the
D-ASIC via the APWM bus.
The C-ASIC's also provide conditioned input voltages on the TRIG-A/TRIG-B line. One
of these voltages will automatically be selected as trigger source by the T-ASIC.

3.2.2 Trigger Circuit

The T ASIC selects one of the possible trigger sources TRIG-A (Input 1) or TRIG-B
(Input 2). For triggering on transients the selected trigger source signal is processed via
the high pass Trigger Filter (TVOUT-TVSYNC lines). Two adjustable trigger levels are
supplied by the D-ASIC via the PWM FILTERS (TRIGLEV1 and TRIGLEV2 line).
Depending on the selected trigger conditions (- source, - level, - edge, - mode), the
T-ASIC generates the final trigger signal TRIGDT, which is supplied to the D-ASIC.
The TRIG-A input is also used for capacitance measurements (see Section 3.2.1).
The T-ASIC includes a constant current source for resistance and capacitance
measurements. The current is supplied via the GENOUT output and the Ω/F relays to
the unknown resistance Rx or capacitance Cx connected to Input 1. The SENSE signal
senses the voltage across Cx and controls a CLAMP circuit in the T-ASIC. This circuit
limits the voltage on Input 1 at capacitance measurements. The protection circuit
prevents the T-ASIC from being damaged by voltages supplied to the input during
resistance or capacitance measurements.
The T-ASIC contains opamps to derive reference voltages from a 1.23 V reference
source. The gain factors for these opamps are determined by resistors in the REF GAIN
circuit. The reference voltages are supplied to various circuits.
The T-ASIC also controls the Input 1/2 AC/DC input coupling relays, and the Ω/F relay.
Control data for the T-ASIC are provided by the D-ASIC via the SDAT and SCLK serial
communication lines.

3.2.3 Digital Circuit

The D-ASIC includes a micro processor, ADC sample acquisition logic, trigger logic,
display and keyboard control logic, I/O ports, and various other logic circuits.
The instrument software is stored in the 8M FlashROM; the 4M RAM is used for
temporary data storage.
For Voltage and Resistance measurements, the conditioned Input 1/2 voltages are
supplied to the ADC-A and ADC-B ADC. The voltages are sampled, and digitized by
the ADC's. The output data of the ADC's are acquired and processed by the D-ASIC.
For capacitance measurements the pulse width of the T-ASIC output signal ALLTRIG,
which is proportional to the unknown capacitance, is counted by the D-ASIC.
The DPWM-BUS (Digital Pulse Width Modulation) supplies square wave signals with a
variable duty cycle to the PWM FILTERS circuit (RC filters). The outgoing
APWM-BUS (Analog PWM) provides analog signals of which the amplitude is
controlled by the D-ASIC. These voltages are used to control e.g. the trace positions
(C-ASIC), the trigger levels (T-ASIC), and the battery charge current (P-ASIC).
In random sampling mode (Scope mode time base faster than 1 µs/d), a trace is built-up
from several acquisition cycles. During each acquisition, a number of trace samples are
placed as pixels in the LCD. The RANDOMIZE circuit takes care that the starting
moment of each acquisition cycle (trigger release signal HOLDOFF goes low) is random.
Circuit Descriptions
3.2 Block Diagram
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