Table of Contents
Advertisement
A
Oscilloscope Block Diagram and Theory of Operation
of the ADC. If inputting a very high level input signal, you would typically
set the V/div setting to a relatively high setting. Using a high V/div setting,
the attenuator stage would first attenuate the input signal (gain < 1) to get
it within the dynamic range of the amplifier, and then the amplifier may
further attenuate the signal (gain <1) to get it within the dynamic range of
the ADC.
Note that when you select a specific V/div setting, the scope automatically
determines the required amount of attenuation in the attenuator block and
the required amount of gain (or possibly additional attenuation) in the
amplifier block. You can think of the attenuator block, DC Offset block,
and amplifier block as a single block of analog input signal conditioning
that linearly conditions a signal that is representative of the input signal
to be within the dynamic range of the ADC block based on the V/div and
offset setting of that particular channel of the scope.
Trigger Comparator and Trigger Logic Blocks
The purpose of the trigger comparator and trigger logic blocks are to
establish a unique point in time on the input signal (or combination of
multiple input signals) upon which to establish a synchronized acquisition.
Let's assume that your input signal is a sine wave and that you want to
trigger acquisitions on the rising edge of the sine wave at the 50% level. In
this case, the non- inverted output of the trigger comparator would be a
square wave with a 50% duty cycle. If you set the trigger level above the
50% level, then the non- inverted output of the trigger comparator would
be less than 50%. Alternatively, if you set the trigger level below the 50%
level, then the non- inverted output would be greater than 50%. Assuming
that triggering is to be based on just a positive edge crossing of a single
channel, the trigger logic block would pass the non- inverted output of the
trigger comparator to the timebase block. If you have selected to trigger on
a negative edge crossing of a single channel, then the trigger logic block
would pass the inverted output of the trigger comparator to the timebase
block. The timebase block then uses the rising edge of the trigger signal as
the unique synchronization point in time. Also note that triggering can be
based on many other variables including time- qualification, as well as a
combination of input signals from multiple input channels.
Timebase and Acquisition Memory Blocks
The timebase block controls when ADC sampling is started and stopped
relative to the trigger event. In addition, the timebase block controls the
ADCs sample rate based on the scope's available acquisition memory
depth and the timebase setting. For example, let's assume that the scope
has been set up to trigger at exactly center screen (default setting) using a
90
2000 X-Series Oscilloscopes Advanced Training Guide
Advertisement
Table of Contents
