External Cache (Cpu Cache); Ecc/Parity Mode Selection - Acer M9N System User Manual

3.3.2

External Cache (CPU Cache)

This parameter enables or disables the second-level cache memory.
Cache Scheme
This parameter allows you to select
for the cache mode.
Write back
memory when there is a write instruction. It updates the memory only
when there is an inconsistency between the cache and the memory.
updates both the cache and the memory whenever
Write through
there is a write instruction.
3.3.3

ECC/Parity Mode Selection

This parameter allows you to select
option allows single-bit error detection and automatic correction.
ECC
The automatic correction depends on the setting of the parameter
Operation of ECC. See section 3.3.4 for details.
ECC also detects multiple-bit errors but does not correct them.
Instead, it issues a non-maskable interrupt (NMI) signaling the
operating system of the multiple-bit error detection.
The option allows parity check. If it detects any parity errors,
Parity
it sets up the parity error flag in the chipset.
operating system of the parity error detection.
Fast-page mode SIMMs with parity support both ECC and parity
mode. EDO SIMMs with parity support only ECC mode.
Both the ECC and parity check features
require parity SIMMs. You must disable this
parameter if you installed SIMMs without
parity.
3-12
Write back or Write through
updates the cache but not the
, , or
ECC Parity Disabled
This signals the
User's Guide
. The