Interrupt Signals - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Interrupt Signals

Table 5-10
and are automatically asserted. All interrupts, required by the
delivered with the core, are cleared by software access to an associated configuration
register. It is recommended that these interrupts are routed to the input of an EDK
Interrupt Controller module as part of the embedded processor subsystem.
Table 5-10: Interrupt Signals
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
defines the interrupt signals asserted by the core. All interrupts are active high
Signal
interrupt_ptp_timer
interrupt_ptp_tx
interrupt_ptp_rx
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Direction
Output This interrupt is asserted every 1/128
second as measured by the
as a timer for the PTP software algorithms.
Output This is asserted following the transmission
of any PTP packet from the
Buffers."
Output This is asserted following the reception of
any PTP packet into the
Buffers."
Core Interfaces
"Software Drivers"
Description
"RTC." This acts
"Tx PTP Packet
"Rx PTP Packet
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