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System Integration
As described in
core can be generated in one of two formats:
•
•
•
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
The Ethernet AVB Endpoint core should be generated in the
Format".
The Ethernet AVB Endpoint core can be connected to the following Ethernet MACs from
the CORE Generator LogiCORE IP library:
•
•
Please also refer to individual product documentation.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 4, "Generating the Core"
"Standard CORE Generator Format"
This option will deliver the core in the standard CORE Generator™ output format, as
used by many other cores including previous versions of this core and all other
Ethernet LogiCORE™ IP solutions.
When generated in this format, the core is designed to interface to the LogiCORE IP
Tri-Mode Ethernet MAC or the LogiCORE IP Embedded Tri-Mode Ethernet MAC
wrappers. Refer to
"Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs"
of this chapter.
"EDK pcore Format"
This option will deliver the core in the standard pcore format, suitable for directly
importing into the Xilinx Embedded Development Kit (EDK) environment.
When generated in this format, the core is designed to interface to the XPS LocalLink
Tri-Mode Ethernet MAC (xps_ll_temac). Refer to
Mode Ethernet MAC"
section of this chapter.
The Ethernet AVB hardware can also be generated as part of the AXI_Ethernet
LogiCORE by setting the AXI_Ethernet parameter C_AVB=1. See
AXI Ethernet MAC"
section of this chapter.
"LogiCORE IP Tri-Mode Ethernet MAC (Soft
Spartan-3E, Spartan-3A, Spartan-3A DSP, Spartan-6, Virtex®-5 and Virtex-6 devices.
"LogiCORE IP Embedded Tri-Mode Ethernet
and Virtex-6 devices.
www.xilinx.com
Chapter 12
and
Chapter 5, "Core
Architecture", the
"Using the Xilinx XPS LocalLink Tri-
the"Using the Xilinx
"Standard CORE Generator
Core)", available for all Spartan®-3,
MACs", available in selected Virtex-5
section
111
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