Reading The Status Register - HP E1399A User Manual

Reading the Status
Register
Chapter 3
For example, assume you need to use up to 8 bits of the status register. To
latch your status data and then read the 8-bit contents of the status register
onto the backplane, you must implement the following signal and control
lines:
1. Address the module correctly by placing the data shown in Table 3-2
on the backplane address lines:
Table 3-2. Backplane Address Lines - Status Register
Line(s) Data Required
Lines A1-A3 Must be set low/high/low (010) to select the BASE+4 enable
line. BASE+4 provides one half of the enable function for line
driver U7 (See Table 2-2 in Chapter 2).
Lines A4, A5 Must both be low (0) to enable 3-to-8 line decoder U8.
Lines A6-A13 Must equal the logical address of the module as set on DIP
switch SP1.
Lines A14, A15 Must always be set high (1) to access the upper 16K of address
space.
Lines AM0-AM5 Must be set to either hexadecimal 29 (101001) or hexadecimal
2D (10 1101). Refer to the VMEbus Specification and the
VXIbus Specification (Rule C.2.10)
Line LWORD* Must always be set high (false) since this is a D16 device. (short
word transfer = 16 bits or less).
2. This is a read operation, so WRITE* must remain high (false) to
provide the second half of the U14 enable function.
3. Set IACK* high (false) to enable address equality detector U18.
4. Set both data strobes DS0* and DS1* low (true) to indicate a 16-bit
data transfer.
Figure 3-2 shows timing required for the Interface IC (U6) control and
signal lines.
Using the HP E1399A 39