MSI K8MM3 Series User Manual page 51

PCI1/2 Master 0 WS Write
W hen [Enabled], writes to the PCI bus are executed with zero wait states.
Setting options: [Enabled], [Disabled].
PCI1/PCI2 Post Write
You can enable or disable the ability of the chipset to use a buffer for posted
writes initiated on the PCI bus. Setting options: [Disabled], [Enabled].
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay trans-
actions cycles. Select [Enabled] to support compliance with PCI specification
version 2.1.
VLink Data Rate
Use this item to select the VLink Data Rate. Setting options: [8X], [4X].
BIOS Setup
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