Acer TravelMate 6493 Series Service Manual page 33

Item
Serial BUS Type
Features
Chapter 1
TI-TSB43AB22A 1394 Function
Fully compliant with provisions of IEEE Std 1394-1995 for a high-
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performance serial bus1 and IEEE Std 1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std
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1394
Compliant with Intel Mobile Power Guideline 2000
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Full IEEE Std 1394a-2000 support includes: connection debounce,
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arbitrated short reset, multispeed concatenation, arbitration acceleration,
fly-by concatenation, and port disable/suspend/resume
Power-down features to conserve energy in battery-powered
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applications include: automatic device power down during suspend, PCI
power management for link-layer, and inactive ports powered down
Ultralow-power sleep mode
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Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s,
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200M bits/s, and 400M bits/s
Cable power presence monitoring
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Separate cable bias (TPBIAS) for each port
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1.8-V core logic with universal PCI interfaces compatible with 3.3-V and
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5-V PCI signaling environments
Physical write posting of up to three outstanding transactions
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PCI burst transfers and deep FIFOs to tolerate large host latency
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PCI_CLKRUN protocol
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External cycle timer control for customized synchronization
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Extended resume signaling for compatibility with legacy DV components
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PHY-Link logic performs system initialization and arbitration functions
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PHY-Link encode and decode functions included for data-strobe bit level
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encoding
PHY-Link incoming data resynchronized to local clock
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Low-cost 24.576-MHz crystal provides transmit and receive data at
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100M bits/s, 200M bits/s, and 400M bits/s
Node power class information signaling for system power management
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Serial ROM interface supports 2-wire serial EEPROM devices
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Two general-purpose I/Os
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Register bits give software control of contender bit, power class bits, link
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active control bit, and IEEE Std 1394a-2000 features
Fabricated in advanced low-power CMOS process
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PCI and CardBus register support
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Isochronous receive dual-buffer mode
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Out-of-order pipelining for asynchronous transmit requests
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Register access fail interrupt when the PHY SCLK is not active
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PCI power-management D0, D1, D2, and D3 power states
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Initial bandwidth available and initial channels available registers
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PME support per 1394 Open Host Controller Interface Specification
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Specification
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