The Sis 620/5595 Chip Set (Vei 7 Pcs); The Sis 620 Chip - HP Vectra VEi7 Technical Reference Manual

The SiS 620/5595 Chip Set (VEi 7 PCs)

The SiS 620/5595 chip set is used in conjunction with a Socket 370
Celeron processor. The SiS 620/5595 chip set is comprised of two chips:
the SiS 620 host chip and the SiS 5595 PCI/ISA bridge chip.
•
•

The SiS 620 Chip

The SiS620 integrates the host bus interface, the DRAM controller, the
IDE controller, the PCI interface, 2D/3D Graphics accelerator and video
playback accelerator. The SiS 620 is contained in a Ball Grid Array
(BGA) package, giving a smaller footprint and higher reliability.
Features of the SiS 620 chip
PL Bus Interface
The SiS 620 chip monitors each cycle that is initiated by the processor,
and forwards to the PCI bus those that are not targeted at the local
memory. It translates PL (Processor Local) bus cycles into PCI bus
cycles.
The chip can support one Celeron processor at a Front Side Bus clock
frequency of 66 MHz.
PCI Bus Interface
The PCI interface is PCI2.2 compliant and supports up to 4 PCI masters.
The built-in PCI arbiter uses a rotating priority arbitration scheme with
guaranteed minimum access time for PCI masters, providing fair access
and low latency for each PCI master.
The SiS 620 is the bridge between three buses: the Processor Local
Bus (GTL+, also referred to as the Host, or Front Side Bus), the main
memory bus, and the PCI bus.
The SiS 5595 chip is the bridge between three buses: the PCI bus, the
SM bus and the ISA bus. In addition, it contains the USB controller
and Power Management logic.
Core Components and Technologies
Chip Sets
17