HP Vectra VEi7 Technical Reference Manual page 15

Features of the Intel PXII4E PCI-ISA Bridge Chip
PCI Bus Interface
This part of the chip is responsible for transferring data between the
PCI bus and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-
PCI bus cycle translation. It supports the Plug-and-Play mechanism.
Data buffers are provided, to isolate the PCI and ISA buses.
ISA Bus Interface
As well as accepting cycles from the PCI bus interface, and translating
them for the ISA bus, the ISA bus interface also requests the PCI
master bridge to generate PCI cycles on behalf of a DMA or ISA master.
The ISA bus interface contains a standard ISA bus controller and data
buffering logic. It can directly support six ISA slots without external
data or address buffering.
SMBus Controller
The System Management (SM) bus is a two-wire serial bus provided by
the PIIX4E controller. It runs at a maximum of 16 kHz. The bus monitors
some of the hardware functions of the main board, both during boot-up
and run-time. All access to the SM bus is handled by the main processor,
via the PIIX4E SM bus registers.
IDE Controller
The PCI master/slave IDE controller supports four devices, two on
each of two channels.
USB Controller
The PCI USB (Universal Serial Bus) controller, supports two stacked
USB connectors on the back panel. These ports are built into the PIIX4E
controller as standard USB ports.
Ultra DMA Controller
The seven channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while
channels 5 to 7 are for 16-bit devices. The channels can be programmed
for any of the four transfer modes: the three active modes (single,
demand and block), can perform three different types of transfer: read,
write and verify. The address generation circuitry supports 24-bit
addresses for DMA devices.
Core Components and Technologies
Chip Sets
15