HP Vectra VEi7 Technical Reference Manual page 16

Chip Sets
Interrupt Controller
The interrupt controller incorporates the functionality of two 82C59
interrupt controllers. The two controllers are cascaded, supporting 15
interrupts (edge/level triggered).
Counter / Timer
The chip contains a three-channel 82C54 counter/timer. The counters
use a division of the 14.318 MHz OSC input as the clock source.
For tips on where to find more information on the Intel 440ZX AGPset,
refer to the bibliography at the beginning of this document.
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Core Components and Technologies