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1.5 Intel
955X Chipset
The Intel 955X chipset consists of the following devices:
•
Intel 82955X Memory Controller Hub (MCH) with Direct Media Interface (DMI) interconnect
•
Intel 82801GR I/O Controller Hub (ICH7-R) with DMI interconnect
The MCH is a centralized controller for the system bus, the memory bus, the PCI Express bus, and
the DMI interconnect. The ICH7-R is a centralized controller for the board's I/O paths.
For information about
The Intel 955X chipset
Resources used by the chipset
1.5.1 USB
The board supports up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and
EHCI-compatible drivers.
The ICH7-R provides the USB controller for all ports. The port arrangement is as follows:
•
Four ports are implemented with dual stacked back panel connectors adjacent to the audio
connectors
•
Four ports are routed to two separate front panel USB connectors
NOTES
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
For information about
The location of the USB connectors on the back panel
The location of the front panel USB connectors
1.5.2 IDE Support
The board provides five IDE interface connectors:
•
One parallel ATA IDE connector that supports two devices
•
Four serial ATA IDE connectors that support one device per connector
1.5.2.1
Parallel ATE IDE Interface
The ICH7-R's Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface.
The Parallel ATA IDE interface supports the following modes:
•
Programmed I/O (PIO): processor controls data transfer.
•
8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
•
Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
•
ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
Product Description
Refer to
http://developer.intel.com/
Chapter 2
Refer to
Figure 18, page 53
Figure 19, page 54
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