Real-Time Clock, Cmos Sram, And Battery; Pci Express Connectors - Intel BLKD915GAGL Technical Product Specification

Intel Desktop Board D915GAV/D915GAG Technical Product Specification
1.7.3.3 SCSI Hard Drive Activity LED Connector (Optional)
The SCSI hard drive activity LED connector is a 1 x 2-pin connector that allows an add-in
hard drive controller to use the same LED as the onboard IDE controller. For proper operation, this
connector should be wired to the LED output of the add-in hard drive controller. The LED
indicates when data is being read from, or written to, either the add-in hard drive controller or the
onboard IDE controller (Parallel ATA or Serial ATA).
For information about
The location of the SCSI hard drive activity LED connector on the D915GAV board
The location of the SCSI hard drive activity LED connector on the D915GAG board
The signal names of the SCSI hard drive activity LED connector

1.7.4 Real-Time Clock, CMOS SRAM, and Battery

A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
RAM at power-on.

1.8 PCI Express Connectors

The boards provide the following PCI Express connectors:
•
One PCI Express x16 connector supporting simultaneous transfer speeds up to 8 GBytes/sec
•
Two PCI Express x1 connectors. The x1 interfaces support simultaneous transfer speeds up to
500 MBytes/sec
The PCI Express interface supports the PCI Conventional bus configuration mechanism so that the
underlying PCI Express architecture is compatible with PCI Conventional compliant operating
systems. Additional features of the PCI Express interface include the following:
•
Support for the PCI Express enhanced configuration mechanism
•
Automatic discovery, link training, and initialization
•
Support for Active State Power Management (ASPM)
•
SMBus 2.0 support
•
Wake# signal supporting wake events from ACPI S1, S3, S4, or S5
•
Software compatible with the PCI Power Management Event (PME) mechanism defined in the
PCI Power Management Specification Rev. 1.1
30
Refer to
Figure 19, page 66
Figure 20, page 68
Table 27, page 71